Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) |	gen_except.sa 3.7 1/16/92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) |	gen_except --- FPSP routine to detect reportable exceptions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) |	This routine compares the exception enable byte of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) |	user_fpcr on the stack with the exception status byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) |	of the user_fpsr.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) |	Any routine which may report an exceptions must load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) |	the stack frame in memory with the exceptional operand(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) |	Priority for exceptions is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) |	Highest:	bsun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) |			snan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) |			operr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) |			ovfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) |			unfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) |			dz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) |			inex2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) |	Lowest:		inex1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) |	Note: The IEEE standard specifies that inex2 is to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) |	reported if ovfl occurs and the ovfl enable bit is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) |	set but the inex2 enable bit is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) |		Copyright (C) Motorola, Inc. 1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) |			All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) |       For details on the license for this file, please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) |       file, README, in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) GEN_EXCEPT:    |idnt    2,1 | Motorola 040 Floating Point Software Package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	|section 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include "fpsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	|xref	real_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	|xref	fpsp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	|xref	fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) exc_tbl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	.long	bsun_exc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.long	commonE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	.long	commonE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	.long	ovfl_unfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.long	ovfl_unfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.long	commonE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.long	commonE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.long	commonE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	.long	no_match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.global	gen_except
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) gen_except:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	cmpib	#IDLE_SIZE-4,1(%a7)	|test for idle frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	beq	do_check		|go handle idle frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	cmpib	#UNIMP_40_SIZE-4,1(%a7)	|test for orig unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	beqs	unimp_x			|go handle unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	cmpib	#UNIMP_41_SIZE-4,1(%a7)	|test for rev unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	beqs	unimp_x			|go handle unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	cmpib	#BUSY_SIZE-4,1(%a7)	|if size <> $60, fmt error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	bnel	fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	leal	BUSY_SIZE+LOCAL_SIZE(%a7),%a1 |init a1 so fpsp.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) |					;equates will work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) | Fix up the new busy frame with entries from the unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	movel	ETEMP_EX(%a6),ETEMP_EX(%a1) |copy etemp from unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	movel	ETEMP_HI(%a6),ETEMP_HI(%a1) |frame to busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	movel	ETEMP_LO(%a6),ETEMP_LO(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	movel	CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	movel	CMDREG1B(%a6),%d0		|fix cmd1b to make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	andl	#0x03c30000,%d0		|work for cmd3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	bfextu	CMDREG1B(%a6){#13:#1},%d1	|extract bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	lsll	#5,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	orl	%d1,%d0			|put it in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	bfextu	CMDREG1B(%a6){#10:#3},%d1	|extract bit 3,4,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	lsll	#2,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	orl	%d1,%d0			|put them in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	movel	%d0,CMDREG3B(%a1)		|in the busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) | Or in the FPSR from the emulation with the USER_FPSR on the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	fmovel	%FPSR,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	orl	%d0,USER_FPSR(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	movel	USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	orl	#sx_mask,E_BYTE(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	bra	do_clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) | Frame is an unimp frame possible resulting from an fmove <ea>,fp0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) | that caused an exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) | a1 is modified to point into the new frame allowing fpsp equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) | to be valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unimp_x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	cmpib	#UNIMP_40_SIZE-4,1(%a7)	|test for orig unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	bnes	test_rev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	leal	UNIMP_40_SIZE+LOCAL_SIZE(%a7),%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	bras	unimp_con
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) test_rev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	cmpib	#UNIMP_41_SIZE-4,1(%a7)	|test for rev unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	bnel	fpsp_fmt_error		|if not $28 or $30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	leal	UNIMP_41_SIZE+LOCAL_SIZE(%a7),%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unimp_con:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) | Fix up the new unimp frame with entries from the old unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	movel	CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | Or in the FPSR from the emulation with the USER_FPSR on the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	fmovel	%FPSR,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	orl	%d0,USER_FPSR(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	bra	do_clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) | Frame is idle, so check for exceptions reported through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | USER_FPSR and set the unimp frame accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | A7 must be incremented to the point before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | idle fsave vector to the unimp vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) do_check:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	addl	#4,%a7			|point A7 back to unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | Or in the FPSR from the emulation with the USER_FPSR on the stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	fmovel	%FPSR,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	orl	%d0,USER_FPSR(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) | On a busy frame, we must clear the nmnexc bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	cmpib	#BUSY_SIZE-4,1(%a7)	|check frame type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bnes	check_fr		|if busy, clr nmnexc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	clrw	NMNEXC(%a6)		|clr nmnexc & nmcexc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	btstb	#5,CMDREG1B(%a6)		|test for fmove out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	bnes	frame_com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	movel	USER_FPSR(%a6),FPSR_SHADOW(%a6) |set exc bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	orl	#sx_mask,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	bras	frame_com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) check_fr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	cmpb	#UNIMP_40_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	beqs	frame_com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	clrw	NMNEXC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) frame_com:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	moveb	FPCR_ENABLE(%a6),%d0	|get fpcr enable byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	andb	FPSR_EXCEPT(%a6),%d0	|and in the fpsr exc byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	bfffo	%d0{#24:#8},%d1		|test for first set bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	leal	exc_tbl,%a0		|load jmp table address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	subib	#24,%d1			|normalize bit offset to 0-8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	movel	(%a0,%d1.w*4),%a0		|load routine address based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) |					;based on first enabled exc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	jmp	(%a0)			|jump to routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) | Bsun is not possible in unimp or unsupp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bsun_exc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bra	do_clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) | The typical work to be done to the unimp frame to report an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) | exception is to set the E1/E3 byte and clr the U flag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | commonE1 does this for E1 exceptions, which are snan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | operr, and dz.  commonE3 does this for E3 exceptions, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) | are inex2 and inex1, and also clears the E1 exception bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) | left over from the unimp exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) commonE1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	bsetb	#E1,E_BYTE(%a6)		|set E1 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	bra	commonE			|go clean and exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) commonE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	tstb	UFLG_TMP(%a6)		|test flag for unsup/unimp state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	bnes	unsE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) uniE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	bsetb	#E3,E_BYTE(%a6)		|set E3 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	bclrb	#E1,E_BYTE(%a6)		|clr E1 from unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bra	commonE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) unsE3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	tstb	RES_FLG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	bnes	unsE3_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsE3_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	bsetb	#E3,E_BYTE(%a6)		|set E3 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsE3_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	bclrb	#E1,E_BYTE(%a6)		|clr E1 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	movel	CMDREG1B(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	andl	#0x03c30000,%d0		|work for cmd3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	bfextu	CMDREG1B(%a6){#13:#1},%d1	|extract bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	lsll	#5,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	orl	%d1,%d0			|put it in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	bfextu	CMDREG1B(%a6){#10:#3},%d1	|extract bit 3,4,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	lsll	#2,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	orl	%d1,%d0			|put them in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	movel	%d0,CMDREG3B(%a6)		|in the busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) commonE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	bclrb	#UFLAG,T_BYTE(%a6)	|clr U flag from unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	bra	do_clean		|go clean and exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) | No bits in the enable byte match existing exceptions.  Check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) | the case of the ovfl exc without the ovfl enabled, but with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) | inex2 enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) no_match:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	btstb	#inex2_bit,FPCR_ENABLE(%a6) |check for ovfl/inex2 case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	beqs	no_exc			|if clear, exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	btstb	#ovfl_bit,FPSR_EXCEPT(%a6) |now check ovfl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	beqs	no_exc			|if clear, exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	bras	ovfl_unfl		|go to unfl_ovfl to determine if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) |					;it is an unsupp or unimp exc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) | No exceptions are to be reported.  If the instruction was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) | unimplemented, no FPU restore is necessary.  If it was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) | unsupported, we must perform the restore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) no_exc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	tstb	UFLG_TMP(%a6)	|test flag for unsupp/unimp state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	beqs	uni_no_exc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) uns_no_exc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	tstb	RES_FLG(%a6)	|check if frestore is needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	bne	do_clean	|if clear, no frestore needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) uni_no_exc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	moveml	USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	fmovemx USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	unlk	%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	bra	finish_up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) | Unsupported Data Type Handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) | Ovfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) |   An fmoveout that results in an overflow is reported this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) | Unfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) |   An fmoveout that results in an underflow is reported this way.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) | Unimplemented Instruction Handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) | Ovfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) |   Only scosh, setox, ssinh, stwotox, and scale can set overflow in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) |   this manner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) | Unfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) |   Stwotox, setox, and scale can set underflow in this manner.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) |   Any of the other Library Routines such that f(x)=x in which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) |   x is an extended denorm can report an underflow exception.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) |   It is the responsibility of the exception-causing exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) |   to make sure that WBTEMP is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) |   The exceptional operand is in FP_SCR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ovfl_unfl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	tstb	UFLG_TMP(%a6)	|test flag for unsupp/unimp state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	beqs	ofuf_con
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) | The caller was from an unsupported data type trap.  Test if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) | caller set CU_ONLY.  If so, the exceptional operand is expected in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) | FPTEMP, rather than WBTEMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	tstb	CU_ONLY(%a6)		|test if inst is cu-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	beq	unsE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) |	move.w	#$fe,CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	clrb	CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	bsetb	#E1,E_BYTE(%a6)		|set E1 exception flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	movew	ETEMP_EX(%a6),FPTEMP_EX(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	movel	ETEMP_HI(%a6),FPTEMP_HI(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	movel	ETEMP_LO(%a6),FPTEMP_LO(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	bsetb	#fptemp15_bit,DTAG(%a6)	|set fpte15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bclrb	#UFLAG,T_BYTE(%a6)	|clr U flag from unimp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	bra	do_clean		|go clean and exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ofuf_con:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	moveb	(%a7),VER_TMP(%a6)	|save version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	cmpib	#BUSY_SIZE-4,1(%a7)	|check for busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	beqs	busy_fr			|if unimp, grow to busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	cmpib	#VER_40,(%a7)		|test for orig unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	bnes	try_41			|if not, test for rev frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	moveql	#13,%d0			|need to zero 14 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	bras	ofuf_fin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) try_41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	cmpib	#VER_41,(%a7)		|test for rev unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	bnel	fpsp_fmt_error		|if neither, exit with error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	moveql	#11,%d0			|need to zero 12 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ofuf_fin:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	clrl	(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) loop1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	clrl	-(%a7)			|clear and dec a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	dbra	%d0,loop1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	moveb	VER_TMP(%a6),(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	moveb	#BUSY_SIZE-4,1(%a7)		|write busy fmt word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) busy_fr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	movel	FP_SCR1(%a6),WBTEMP_EX(%a6)	|write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	movel	FP_SCR1+4(%a6),WBTEMP_HI(%a6)	|exceptional op to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	movel	FP_SCR1+8(%a6),WBTEMP_LO(%a6)	|wbtemp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	bsetb	#E3,E_BYTE(%a6)			|set E3 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	bclrb	#E1,E_BYTE(%a6)			|make sure E1 is clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	bclrb	#UFLAG,T_BYTE(%a6)		|clr U flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	movel	USER_FPSR(%a6),FPSR_SHADOW(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	orl	#sx_mask,E_BYTE(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	movel	CMDREG1B(%a6),%d0		|fix cmd1b to make it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	andl	#0x03c30000,%d0		|work for cmd3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	bfextu	CMDREG1B(%a6){#13:#1},%d1	|extract bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	lsll	#5,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	orl	%d1,%d0			|put it in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	bfextu	CMDREG1B(%a6){#10:#3},%d1	|extract bit 3,4,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	lsll	#2,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	swap	%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	orl	%d1,%d0			|put them in the right place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	movel	%d0,CMDREG3B(%a6)		|in the busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) | Check if the frame to be restored is busy or unimp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) |** NOTE *** Bug fix for errata (0d43b #3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) | If the frame is unimp, we must create a busy frame to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) | fix the bug with the nmnexc bits in cases in which they
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) | are set by a previous instruction and not cleared by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) | the save. The frame will be unimp only if the final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) | instruction in an emulation routine caused the exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) | by doing an fmove <ea>,fp0.  The exception operand, in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) | internal format, is in fptemp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) do_clean:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	cmpib	#UNIMP_40_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	bnes	do_con
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	moveql	#13,%d0			|in orig, need to zero 14 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	bras	do_build
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) do_con:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	cmpib	#UNIMP_41_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	bnes	do_restore		|frame must be busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	moveql	#11,%d0			|in rev, need to zero 12 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) do_build:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	moveb	(%a7),VER_TMP(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	clrl	(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) loop2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	clrl	-(%a7)			|clear and dec a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	dbra	%d0,loop2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) | Use a1 as pointer into new frame.  a6 is not correct if an unimp or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) | busy frame was created as the result of an exception on the final
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) | instruction of an emulation routine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) | We need to set the nmcexc bits if the exception is E1. Otherwise,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) | the exc taken will be inex2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	leal	BUSY_SIZE+LOCAL_SIZE(%a7),%a1	|init a1 for new frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	moveb	VER_TMP(%a6),(%a7)	|write busy fmt word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	moveb	#BUSY_SIZE-4,1(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	movel	FP_SCR1(%a6),WBTEMP_EX(%a1)	|write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	movel	FP_SCR1+4(%a6),WBTEMP_HI(%a1)	|exceptional op to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	movel	FP_SCR1+8(%a6),WBTEMP_LO(%a1)	|wbtemp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) |	btst.b	#E1,E_BYTE(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) |	beq.b	do_restore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	bfextu	USER_FPSR(%a6){#17:#4},%d0	|get snan/operr/ovfl/unfl bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	bfins	%d0,NMCEXC(%a1){#4:#4}	|and insert them in nmcexc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	movel	USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	orl	#sx_mask,E_BYTE(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) do_restore:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	moveml	USER_DA(%a6),%d0-%d1/%a0-%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	fmovemx USER_FP0(%a6),%fp0-%fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	fmoveml USER_FPCR(%a6),%fpcr/%fpsr/%fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	frestore (%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	tstb	RES_FLG(%a6)	|RES_FLG indicates a "continuation" frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	beq	cont
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	bsr	bug1384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cont:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	unlk	%a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) | If trace mode enabled, then go to trace handler.  This handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) | cannot have any fp instructions.  If there are fp inst's and an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) | exception has been restored into the machine then the exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) | will occur upon execution of the fp inst.  This is not desirable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) | in the kernel (supervisor mode).  See MC68040 manual Section 9.3.8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) finish_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	btstb	#7,(%a7)		|test T1 in SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	bnes	g_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	btstb	#6,(%a7)		|test T0 in SR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	bnes	g_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	bral	fpsp_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) | Change integer stack to look like trace stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) | The address of the instruction that caused the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) | exception is already in the integer stack (is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) | the same as the saved friar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) | If the current frame is already a 6-word stack then all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) | that needs to be done is to change the vector# to TRACE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) | If the frame is only a 4-word stack (meaning we got here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) | on an Unsupported data type exception), then we need to grow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) | the stack an extra 2 words and get the FPIAR from the FPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) g_trace:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	bftst	EXC_VEC-4(%sp){#0:#4}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	bne	g_easy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	subw	#4,%sp		| make room
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	movel	4(%sp),(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	movel	8(%sp),4(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	subw	#BUSY_SIZE,%sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	fsave	(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	fmovel	%fpiar,BUSY_SIZE+EXC_EA-4(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	frestore (%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	addw	#BUSY_SIZE,%sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) g_easy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	movew	#TRACE_VEC,EXC_VEC-4(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	bral	real_trace
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) |  This is a work-around for hardware bug 1384.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) bug1384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	link	%a5,#0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	fsave	-(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	cmpib	#0x41,(%sp)	| check for correct frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	beq	frame_41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	bgt	nofix		| if more advanced mask, do nada
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) frame_40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	tstb	1(%sp)		| check to see if idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	bne	notidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) idle40:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	clrl	(%sp)		| get rid of old fsave frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)         movel  %d1,USER_D1(%a6)  | save d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	movew	#8,%d1		| place unimp frame instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) loop40:	clrl	-(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	dbra	%d1,loop40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)         movel  USER_D1(%a6),%d1  | restore d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	movel	#0x40280000,-(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	frestore (%sp)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	unlk	%a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) frame_41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	tstb	1(%sp)		| check to see if idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	bne	notidle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) idle41:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	clrl	(%sp)		| get rid of old fsave frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)         movel  %d1,USER_D1(%a6)  | save d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	movew	#10,%d1		| place unimp frame instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) loop41:	clrl	-(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	dbra	%d1,loop41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)         movel  USER_D1(%a6),%d1  | restore d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	movel	#0x41300000,-(%sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	frestore (%sp)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	unlk	%a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) notidle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	bclrb	#etemp15_bit,-40(%a5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	frestore (%sp)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	unlk	%a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) nofix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	frestore (%sp)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	unlk	%a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	|end