Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) |	fpsp.h 3.3 3.3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) |		Copyright (C) Motorola, Inc. 1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) |			All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) |       For details on the license for this file, please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) |       file, README, in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) |	fpsp.h --- stack frame offsets during FPSP exception handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) |	These equates are used to access the exception frame, the fsave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) |	frame and any local variables needed by the FPSP package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) |	All FPSP handlers begin by executing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) |		link	a6,#-LOCAL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) |		fsave	-(a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) |		movem.l	d0-d1/a0-a1,USER_DA(a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) |		fmovem.x fp0-fp3,USER_FP0(a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) |		fmove.l	fpsr/fpcr/fpiar,USER_FPSR(a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) |	After initialization, the stack looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) |	A7 --->	+-------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) |		|	FPU fsave area		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) |		+-------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) |		|	FPSP Local Variables	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) |		|	     including		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) |		|	  saved registers	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) |		+-------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) |	A6 --->	|	Saved A6		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) |		+-------------------------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) |		|	Exception Frame		|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) |		|				|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) |	Positive offsets from A6 refer to the exception frame.  Negative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) |	offsets refer to the Local Variable area and the fsave area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) |	The fsave frame is also accessible from the top via A7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) |	On exit, the handlers execute:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) |		movem.l	USER_DA(a6),d0-d1/a0-a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) |		fmovem.x USER_FP0(a6),fp0-fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) |		fmove.l	USER_FPSR(a6),fpsr/fpcr/fpiar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) |		frestore (a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) |		unlk	a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) |	and then either "bra fpsp_done" if the exception was completely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) |	handled	by the package, or "bra real_xxxx" which is an external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) |	label to a routine that will process a real exception of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) |	type that was generated.  Some handlers may omit the "frestore"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) |	if the FPU state after the exception is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) |	Sometimes the exception handler will transform the fsave area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) |	because it needs to report an exception back to the user.  This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) |	can happen if the package is entered for an unimplemented float
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) |	instruction that generates (say) an underflow.  Alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) |	a second fsave frame can be pushed onto the stack and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) |	handler	exit code will reload the new frame and discard the old.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) |	The registers d0, d1, a0, a1 and fp0-fp3 are always saved and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) |	restored from the "local variable" area and can be used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) |	temporaries.  If a routine needs to change any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) |	of these registers, it should modify the saved copy and let
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) |	the handler exit code restore the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) |----------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) |	Local Variables on the stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.set	LOCAL_SIZE,192		| bytes needed for local variables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.set	LV,-LOCAL_SIZE	| convenient base value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.set	USER_DA,LV+0		| save space for D0-D1,A0-A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.set	USER_D0,LV+0		| saved user D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.set	USER_D1,LV+4		| saved user D1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.set	USER_A0,LV+8		| saved user A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.set	USER_A1,LV+12		| saved user A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.set	USER_FP0,LV+16		| saved user FP0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.set	USER_FP1,LV+28		| saved user FP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.set	USER_FP2,LV+40		| saved user FP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.set	USER_FP3,LV+52		| saved user FP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.set	USER_FPCR,LV+64		| saved user FPCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.set	FPCR_ENABLE,USER_FPCR+2	|	FPCR exception enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	.set	FPCR_MODE,USER_FPCR+3	|	FPCR rounding mode control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	.set	USER_FPSR,LV+68		| saved user FPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	.set	FPSR_CC,USER_FPSR+0	|	FPSR condition code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	.set	FPSR_QBYTE,USER_FPSR+1	|	FPSR quotient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	.set	FPSR_EXCEPT,USER_FPSR+2	|	FPSR exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	.set	FPSR_AEXCEPT,USER_FPSR+3	|	FPSR accrued exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.set	USER_FPIAR,LV+72		| saved user FPIAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.set	FP_SCR1,LV+76		| room for a temporary float value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.set	FP_SCR2,LV+92		| room for a temporary float value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.set	L_SCR1,LV+108		| room for a temporary long value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.set	L_SCR2,LV+112		| room for a temporary long value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.set	STORE_FLG,LV+116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.set	BINDEC_FLG,LV+117		| used in bindec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.set	DNRM_FLG,LV+118		| used in res_func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.set	RES_FLG,LV+119		| used in res_func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.set	DY_MO_FLG,LV+120		| dyadic/monadic flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.set	UFLG_TMP,LV+121		| temporary for uflag errata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.set	CU_ONLY,LV+122		| cu-only flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.set	VER_TMP,LV+123		| temp holding for version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.set	L_SCR3,LV+124		| room for a temporary long value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.set	FP_SCR3,LV+128		| room for a temporary float value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.set	FP_SCR4,LV+144		| room for a temporary float value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.set	FP_SCR5,LV+160		| room for a temporary float value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.set	FP_SCR6,LV+176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) |NEXT		equ	LV+192		;need to increase LOCAL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) |--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) |	fsave offsets and bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) |	Offsets are defined from the end of an fsave because the last 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) |	words of a busy frame are the same as the unimplemented frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.set	CU_SAVEPC,LV-92		| micro-pc for CU (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	.set	FPR_DIRTY_BITS,LV-91		| fpr dirty bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.set	WBTEMP,LV-76		| write back temp (12 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	.set	WBTEMP_EX,WBTEMP		| wbtemp sign and exponent (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.set	WBTEMP_HI,WBTEMP+4	| wbtemp mantissa [63:32] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.set	WBTEMP_LO,WBTEMP+8	| wbtemp mantissa [31:00] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.set	WBTEMP_SGN,WBTEMP+2	| used to store sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.set	FPSR_SHADOW,LV-64		| fpsr shadow reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.set	FPIARCU,LV-60		| Instr. addr. reg. for CU (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.set	CMDREG2B,LV-52		| cmd reg for machine 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.set	CMDREG3B,LV-48		| cmd reg for E3 exceptions (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.set	NMNEXC,LV-44		| NMNEXC (unsup,snan bits only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.set	nmn_unsup_bit,1	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.set	nmn_snan_bit,0	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.set	NMCEXC,LV-43		| NMNEXC & NMCEXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.set	nmn_operr_bit,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.set	nmn_ovfl_bit,6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.set	nmn_unfl_bit,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.set	nmc_unsup_bit,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.set	nmc_snan_bit,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.set	nmc_operr_bit,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.set	nmc_ovfl_bit,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.set	nmc_unfl_bit,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.set	STAG,LV-40		| source tag (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.set	WBTEMP_GRS,LV-40		| alias wbtemp guard, round, sticky
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.set	guard_bit,1		| guard bit is bit number 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.set	round_bit,0		| round bit is bit number 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.set	stag_mask,0xE0		| upper 3 bits are source tag type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.set	denorm_bit,7		| bit determines if denorm or unnorm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.set	etemp15_bit,4		| etemp exponent bit #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.set	wbtemp66_bit,2		| wbtemp mantissa bit #66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	.set	wbtemp1_bit,1		| wbtemp mantissa bit #1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	.set	wbtemp0_bit,0		| wbtemp mantissa bit #0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.set	STICKY,LV-39		| holds sticky bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.set	sticky_bit,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.set	CMDREG1B,LV-36		| cmd reg for E1 exceptions (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.set	kfact_bit,12		| distinguishes static/dynamic k-factor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) |					;on packed move outs.  NOTE: this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) |					;equate only works when CMDREG1B is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) |					;a register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set	CMDWORD,LV-35		| command word in cmd1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.set	direction_bit,5		| bit 0 in opclass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set	size_bit2,12		| bit 2 in size field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.set	DTAG,LV-32		| dest tag (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.set	dtag_mask,0xE0		| upper 3 bits are dest type tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.set	fptemp15_bit,4		| fptemp exponent bit #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.set	WB_BYTE,LV-31		| holds WBTE15 bit (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.set	wbtemp15_bit,4		| wbtemp exponent bit #15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.set	E_BYTE,LV-28		| holds E1 and E3 bits (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.set	E1,2		| which bit is E1 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.set	E3,1		| which bit is E3 flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.set	SFLAG,0		| which bit is S flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.set	T_BYTE,LV-27		| holds T and U bits (1 byte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.set	XFLAG,7		| which bit is X flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.set	UFLAG,5		| which bit is U flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.set	TFLAG,4		| which bit is T flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	.set	FPTEMP,LV-24		| fptemp (12 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.set	FPTEMP_EX,FPTEMP		| fptemp sign and exponent (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	.set	FPTEMP_HI,FPTEMP+4	| fptemp mantissa [63:32] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	.set	FPTEMP_LO,FPTEMP+8	| fptemp mantissa [31:00] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	.set	FPTEMP_SGN,FPTEMP+2	| used to store sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.set	ETEMP,LV-12		| etemp (12 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.set	ETEMP_EX,ETEMP		| etemp sign and exponent (2 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.set	ETEMP_HI,ETEMP+4		| etemp mantissa [63:32] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.set	ETEMP_LO,ETEMP+8		| etemp mantissa [31:00] (4 bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.set	ETEMP_SGN,ETEMP+2		| used to store sign
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.set	EXC_SR,4		| exception frame status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.set	EXC_PC,6		| exception frame program counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.set	EXC_VEC,10		| exception frame vector (format+vector#)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.set	EXC_EA,12		| exception frame effective address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) |--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) |	FPSR/FPCR bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.set	neg_bit,3	|  negative result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.set	z_bit,2	|  zero result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.set	inf_bit,1	|  infinity result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.set	nan_bit,0	|  not-a-number result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set	q_sn_bit,7	|  sign bit of quotient byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.set	bsun_bit,7	|  branch on unordered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.set	snan_bit,6	|  signalling nan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.set	operr_bit,5	|  operand error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.set	ovfl_bit,4	|  overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.set	unfl_bit,3	|  underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.set	dz_bit,2	|  divide by zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.set	inex2_bit,1	|  inexact result 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.set	inex1_bit,0	|  inexact result 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.set	aiop_bit,7	|  accrued illegal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.set	aovfl_bit,6	|  accrued overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.set	aunfl_bit,5	|  accrued underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.set	adz_bit,4	|  accrued divide by zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.set	ainex_bit,3	|  accrued inexact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) |	FPSR individual bit masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.set	neg_mask,0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.set	z_mask,0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.set	inf_mask,0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.set	nan_mask,0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.set	bsun_mask,0x00008000	|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.set	snan_mask,0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.set	operr_mask,0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.set	ovfl_mask,0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.set	unfl_mask,0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.set	dz_mask,0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.set	inex2_mask,0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.set	inex1_mask,0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.set	aiop_mask,0x00000080	|  accrued illegal operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.set	aovfl_mask,0x00000040	|  accrued overflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.set	aunfl_mask,0x00000020	|  accrued underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.set	adz_mask,0x00000010	|  accrued divide by zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.set	ainex_mask,0x00000008	|  accrued inexact
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) |	FPSR combinations used in the FPSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.set	dzinf_mask,inf_mask+dz_mask+adz_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.set	opnan_mask,nan_mask+operr_mask+aiop_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.set	nzi_mask,0x01ffffff	|  clears N, Z, and I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.set	unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.set	unf2inx_mask,unfl_mask+inex2_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.set	ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.set	inx1a_mask,inex1_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.set	inx2a_mask,inex2_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.set	snaniop_mask,nan_mask+snan_mask+aiop_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.set	naniop_mask,nan_mask+aiop_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.set	neginf_mask,neg_mask+inf_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.set	infaiop_mask,inf_mask+aiop_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.set	negz_mask,neg_mask+z_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.set	opaop_mask,operr_mask+aiop_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.set	unfl_inx_mask,unfl_mask+aunfl_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.set	ovfl_inx_mask,ovfl_mask+aovfl_mask+ainex_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) |--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) |	FPCR rounding modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.set	x_mode,0x00	|  round to extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.set	s_mode,0x40	|  round to single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.set	d_mode,0x80	|  round to double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.set	rn_mode,0x00	|  round nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.set	rz_mode,0x10	|  round to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.set	rm_mode,0x20	|  round to minus infinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.set	rp_mode,0x30	|  round to plus infinity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) |--------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) |	Miscellaneous equates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.set	signan_bit,6	|  signalling nan bit in mantissa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.set	sign_bit,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.set	rnd_stky_bit,29	|  round/sticky bit of mantissa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) |				this can only be used if in a data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.set	sx_mask,0x01800000 |  set s and x bits in word $48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.set	LOCAL_EX,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.set	LOCAL_SGN,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.set	LOCAL_HI,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	.set	LOCAL_LO,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	.set	LOCAL_GRS,12	|  valid ONLY for FP_SCR1, FP_SCR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.set	norm_tag,0x00	|  tag bits in {7:5} position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.set	zero_tag,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	.set	inf_tag,0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	.set	nan_tag,0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	.set	dnrm_tag,0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) |	fsave sizes and formats
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.set	VER_4,0x40		|  fpsp compatible version numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) |					are in the $40s {$40-$4f}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.set	VER_40,0x40		|  original version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.set	VER_41,0x41		|  revision version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	.set	BUSY_SIZE,100		|  size of busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	.set	BUSY_FRAME,LV-BUSY_SIZE	|  start of busy frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	.set	UNIMP_40_SIZE,44		|  size of orig unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	.set	UNIMP_41_SIZE,52		|  size of rev unimp frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	.set	IDLE_SIZE,4		|  size of idle frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	.set	IDLE_FRAME,LV-IDLE_SIZE	|  start of idle frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) |	exception vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.set	TRACE_VEC,0x2024		|  trace trap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.set	FLINE_VEC,0x002C		|  real F-line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.set	UNIMP_VEC,0x202C		|  unimplemented
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.set	INEX_VEC,0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.set	dbl_thresh,0x3C01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.set	sgl_thresh,0x3F81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) |