^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) | bugfix.sa 3.2 1/31/91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) | This file contains workarounds for bugs in the 040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) | relating to the Floating-Point Software Package (FPSP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) | Fixes for bugs: 1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) | Bug: 1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) | /* The following dirty_bit clear should be left in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) | * the handler permanently to improve throughput.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) | * The dirty_bits are located at bits [23:16] in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) | * longword $08 in the busy frame $4x60. Bit 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) | * corresponds to FP0, bit 17 corresponds to FP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) | * and so on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) | if (E3_exception_just_serviced) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) | dirty_bit[cmdreg3b[9:7]] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) | }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) | if (fsave_format_version != $40) {goto NOFIX}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) | if !(E3_exception_just_serviced) {goto NOFIX}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) | if (cupc == 0000000) {goto NOFIX}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) | if ((cmdreg1b[15:13] != 000) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) | (cmdreg1b[15:10] != 010001)) {goto NOFIX}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) | if (((cmdreg1b[15:13] != 000) || ((cmdreg1b[12:10] != cmdreg2b[9:7]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) | (cmdreg1b[12:10] != cmdreg3b[9:7])) ) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) | ((cmdreg1b[ 9: 7] != cmdreg2b[9:7]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) | (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) ) {goto NOFIX}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) | /* Note: for 6d43b or 8d43b, you may want to add the following code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) | * to get better coverage. (If you do not insert this code, the part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) | * won't lock up; it will simply get the wrong answer.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) | * Do NOT insert this code for 10d43b or later parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) | *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) | * if (fpiarcu == integer stack return address) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) | * cupc = 0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) | * goto NOFIX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) | * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) | if (cmdreg1b[15:13] != 000) {goto FIX_OPCLASS2}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) | FIX_OPCLASS0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) | if (((cmdreg1b[12:10] == cmdreg2b[9:7]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) | (cmdreg1b[ 9: 7] == cmdreg2b[9:7])) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) | (cmdreg1b[12:10] != cmdreg3b[9:7]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) | (cmdreg1b[ 9: 7] != cmdreg3b[9:7])) { /* xu conflict only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) | /* We execute the following code if there is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) | xu conflict and NOT an nu conflict */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) | /* first save some values on the fsave frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) | stag_temp = STAG[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) | cmdreg1b_temp = CMDREG1B[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) | dtag_temp = DTAG[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) | ete15_temp = ETE15[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) | CUPC[fsave_frame] = 0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) | FRESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) | FSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) | /* If the xu instruction is exceptional, we punt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) | * Otherwise, we would have to include OVFL/UNFL handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) | * code here to get the correct answer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) | if (fsave_frame_format == $4060) {goto KILL_PROCESS}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) | fsave_frame = /* build a long frame of all zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) | fsave_frame_format = $4060; /* label it as long frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) | /* load it with the temps we saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) | STAG[fsave_frame] = stag_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) | CMDREG1B[fsave_frame] = cmdreg1b_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) | DTAG[fsave_frame] = dtag_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) | ETE15[fsave_frame] = ete15_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) | /* Make sure that the cmdreg3b dest reg is not going to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) | * be destroyed by a FMOVEM at the end of all this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) | * If it is, you should move the current value of the reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) | * onto the stack so that the reg will loaded with that value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) | /* All done. Proceed with the code below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) | }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) | etemp = FP_reg_[cmdreg1b[12:10]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) | ete15 = ~ete14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | cmdreg1b[15:10] = 010010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) | clear(bug_flag_procIDxxxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) | FRESTORE and return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) | FIX_OPCLASS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) | if ((cmdreg1b[9:7] == cmdreg2b[9:7]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) | (cmdreg1b[9:7] != cmdreg3b[9:7])) { /* xu conflict only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) | /* We execute the following code if there is an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) | xu conflict and NOT an nu conflict */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) | /* first save some values on the fsave frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) | stag_temp = STAG[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) | cmdreg1b_temp = CMDREG1B[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) | dtag_temp = DTAG[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) | ete15_temp = ETE15[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) | etemp_temp = ETEMP[fsave_frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) | CUPC[fsave_frame] = 0000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) | FRESTORE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) | FSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) | /* If the xu instruction is exceptional, we punt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) | * Otherwise, we would have to include OVFL/UNFL handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) | * code here to get the correct answer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) | if (fsave_frame_format == $4060) {goto KILL_PROCESS}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) | fsave_frame = /* build a long frame of all zeros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) | fsave_frame_format = $4060; /* label it as long frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) | /* load it with the temps we saved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) | STAG[fsave_frame] = stag_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) | CMDREG1B[fsave_frame] = cmdreg1b_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) | DTAG[fsave_frame] = dtag_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) | ETE15[fsave_frame] = ete15_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) | ETEMP[fsave_frame] = etemp_temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | /* Make sure that the cmdreg3b dest reg is not going to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) | * be destroyed by a FMOVEM at the end of all this code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) | * If it is, you should move the current value of the reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) | * onto the stack so that the reg will loaded with that value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) | */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) | /* All done. Proceed with the code below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) | }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) | if (etemp_exponent == min_sgl) etemp_exponent = min_dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) | if (etemp_exponent == max_sgl) etemp_exponent = max_dbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) | cmdreg1b[15:10] = 010101;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) | clear(bug_flag_procIDxxxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) | FRESTORE and return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) | NOFIX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) | clear(bug_flag_procIDxxxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) | FRESTORE and return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) | Copyright (C) Motorola, Inc. 1990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) | All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) | For details on the license for this file, please see the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) | file, README, in this same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) |BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) |section 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #include "fpsp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) |xref fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .global b1238_fix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) b1238_fix:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) | This code is entered only on completion of the handling of an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) | nu-generated ovfl, unfl, or inex exception. If the version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) | number of the fsave is not $40, this handler is not necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) | Simply branch to fix_done and exit normally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) cmpib #VER_40,4(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bne fix_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) | Test for cu_savepc equal to zero. If not, this is not a bug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) | #1238 case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) moveb CU_SAVEPC(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) andib #0xFE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) beq fix_done |if zero, this is not bug #1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) | Test the register conflict aspect. If opclass0, check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) | cu src equal to xu dest or equal to nu dest. If so, go to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) | op0. Else, or if opclass2, check for cu dest equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) | xu dest or equal to nu dest. If so, go to tst_opcl. Else,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) | exit, it is not the bug case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) | Check for opclass 0. If not, go and check for opclass 2 and sgl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) movew CMDREG1B(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) andiw #0xE000,%d0 |strip all but opclass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) bne op2sgl |not opclass 0, check op2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) | Check for cu and nu register conflict. If one exists, this takes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) | priority over a cu and xu conflict.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) cmpb %d0,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) beqs op0 |if equal, continue bugfix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) | Check for cu dest equal to nu dest. If so, go and fix the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) | bug condition. Otherwise, exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) cmpb %d0,%d1 |cmp 1st dest with 3rd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) beqs op0 |if equal, continue bugfix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) | Check for cu and xu register conflict.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cmpb %d0,%d1 |cmp 1st dest with 2nd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) beqs op0_xu |if equal, continue bugfix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) cmpb %d0,%d1 |cmp 1st src with 2nd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) beq op0_xu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) bne fix_done |if the reg checks fail, exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) | We have the opclass 0 situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) op0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) movel #7,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) subl %d0,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) clrl %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bsetl %d1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) fmovemx %d0,ETEMP(%a6) |load source to ETEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) moveb #0x12,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) | Set ETEMP exponent bit 15 as the opposite of ete14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) beq setete15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bclr #etemp15_bit,STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) setete15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bset #etemp15_bit,STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) | We have the case in which a conflict exists between the cu src or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) | dest and the dest of the xu. We must clear the instruction in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) | the cu and restore the state, allowing the instruction in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) | xu to complete. Remember, the instruction in the nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) | was exceptional, and was completed by the appropriate handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) | If the result of the xu instruction is not exceptional, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) | restore the instruction from the cu to the frame and continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) | processing the original exception. If the result is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) | exceptional, we choose to kill the process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) | Items saved from the stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) | $3c stag - L_SCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) | $40 cmdreg1b - L_SCR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) | $44 dtag - L_SCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) | The cu savepc is set to zero, and the frame is restored to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) | fpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) op0_xu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) movel STAG(%a6),L_SCR1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) movel CMDREG1B(%a6),L_SCR2(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) movel DTAG(%a6),L_SCR3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) andil #0xe0000000,L_SCR3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) moveb #0,CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) movel (%a7)+,%d1 |save return address from bsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) frestore (%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) fsave -(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) | Check if the instruction which just completed was exceptional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) cmpw #0x4060,(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) beq op0_xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) | It is necessary to isolate the result of the instruction in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) | xu if it is to fp0 - fp3 and write that value to the USER_FPn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) | locations on the stack. The correct destination register is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) | cmdreg2b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) cmpil #3,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) bgts op0_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) beqs op0_fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) cmpil #1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) blts op0_fp0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) beqs op0_fp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) op0_fp2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) fmovemx %fp2-%fp2,USER_FP2(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bras op0_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) op0_fp1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fmovemx %fp1-%fp1,USER_FP1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bras op0_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) op0_fp0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) fmovemx %fp0-%fp0,USER_FP0(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bras op0_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) op0_fp3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) fmovemx %fp3-%fp3,USER_FP3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) | The frame returned is idle. We must build a busy frame to hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) | the cu state information and setup etemp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) op0_xi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) movel #22,%d0 |clear 23 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) clrl (%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) op0_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) clrl -(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dbf %d0,op0_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) movel #0x40600000,-(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) movel L_SCR1(%a6),STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) movel L_SCR2(%a6),CMDREG1B(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) movel L_SCR3(%a6),DTAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) moveb #0x6,CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) movel %d1,-(%a7) |return bsr return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) bfextu CMDREG1B(%a6){#3:#3},%d0 |get source register no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) movel #7,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) subl %d0,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) clrl %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bsetl %d1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) fmovemx %d0,ETEMP(%a6) |load source to ETEMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) moveb #0x12,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, extended
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) | Set ETEMP exponent bit 15 as the opposite of ete14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) btst #6,ETEMP_EX(%a6) |check etemp exponent bit 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) beq op0_sete15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) bclr #etemp15_bit,STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) op0_sete15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bset #etemp15_bit,STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) | The frame returned is busy. It is not possible to reconstruct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) | the code sequence to allow completion. We will jump to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) | fpsp_fmt_error and allow the kernel to kill the process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) op0_xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) jmp fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) | Check for opclass 2 and single size. If not both, exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) op2sgl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) movew CMDREG1B(%a6),%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) andiw #0xFC00,%d0 |strip all but opclass and size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) bne fix_done |if not, it is not bug 1238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) | Check for cu dest equal to nu dest or equal to xu dest, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) | a cu and nu conflict taking priority an nu conflict. If either,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) | go and fix the bug condition. Otherwise, exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) cmpb %d0,%d1 |cmp 1st dest with 3rd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) beq op2_com |if equal, continue bugfix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) cmpb %d0,%d1 |cmp 1st dest with 2nd dest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) bne fix_done |if the reg checks fail, exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) | We have the case in which a conflict exists between the cu src or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) | dest and the dest of the xu. We must clear the instruction in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) | the cu and restore the state, allowing the instruction in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) | xu to complete. Remember, the instruction in the nu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) | was exceptional, and was completed by the appropriate handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) | If the result of the xu instruction is not exceptional, we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) | restore the instruction from the cu to the frame and continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) | processing the original exception. If the result is also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) | exceptional, we choose to kill the process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) | Items saved from the stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) | $3c stag - L_SCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) | $40 cmdreg1b - L_SCR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) | $44 dtag - L_SCR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) | etemp - FP_SCR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) | The cu savepc is set to zero, and the frame is restored to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) | fpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) op2_xu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) movel STAG(%a6),L_SCR1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) movel CMDREG1B(%a6),L_SCR2(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) movel DTAG(%a6),L_SCR3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) andil #0xe0000000,L_SCR3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) moveb #0,CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) movel ETEMP(%a6),FP_SCR2(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) movel ETEMP_HI(%a6),FP_SCR2+4(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) movel ETEMP_LO(%a6),FP_SCR2+8(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) movel (%a7)+,%d1 |save return address from bsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) frestore (%a7)+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) fsave -(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) | Check if the instruction which just completed was exceptional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cmpw #0x4060,(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) beq op2_xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) | It is necessary to isolate the result of the instruction in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) | xu if it is to fp0 - fp3 and write that value to the USER_FPn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) | locations on the stack. The correct destination register is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) | cmdreg2b.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cmpil #3,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) bgts op2_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) beqs op2_fp3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cmpil #1,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) blts op2_fp0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) beqs op2_fp1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) op2_fp2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) fmovemx %fp2-%fp2,USER_FP2(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) bras op2_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) op2_fp1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) fmovemx %fp1-%fp1,USER_FP1(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bras op2_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) op2_fp0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) fmovemx %fp0-%fp0,USER_FP0(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) bras op2_xi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) op2_fp3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) fmovemx %fp3-%fp3,USER_FP3(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) | The frame returned is idle. We must build a busy frame to hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) | the cu state information and fix up etemp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) op2_xi:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) movel #22,%d0 |clear 23 lwords
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) clrl (%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) op2_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clrl -(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dbf %d0,op2_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) movel #0x40600000,-(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) movel L_SCR1(%a6),STAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) movel L_SCR2(%a6),CMDREG1B(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) movel L_SCR3(%a6),DTAG(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) moveb #0x6,CU_SAVEPC(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) movel FP_SCR2(%a6),ETEMP(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) movel FP_SCR2+4(%a6),ETEMP_HI(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) movel FP_SCR2+8(%a6),ETEMP_LO(%a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) movel %d1,-(%a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) bra op2_com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) | We have the opclass 2 single source situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) op2_com:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) moveb #0x15,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) bfins %d0,CMDREG1B(%a6){#0:#6} |opclass 2, double
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) cmpw #0x407F,ETEMP_EX(%a6) |single +max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bnes case2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) movew #0x43FF,ETEMP_EX(%a6) |to double +max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cmpw #0xC07F,ETEMP_EX(%a6) |single -max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) bnes case3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) movew #0xC3FF,ETEMP_EX(%a6) |to double -max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) case3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cmpw #0x3F80,ETEMP_EX(%a6) |single +min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bnes case4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) movew #0x3C00,ETEMP_EX(%a6) |to double +min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) case4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) cmpw #0xBF80,ETEMP_EX(%a6) |single -min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bne fix_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) movew #0xBC00,ETEMP_EX(%a6) |to double -min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) bra finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) | The frame returned is busy. It is not possible to reconstruct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) | the code sequence to allow completion. fpsp_fmt_error causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) | an fline illegal instruction to be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) | You should replace the jump to fpsp_fmt_error with a jump
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) | to the entry point used to kill a process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) op2_xb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) jmp fpsp_fmt_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) | Enter here if the case is not of the situations affected by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) | bug #1238, or if the fix is completed, and exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fix_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) rts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) |end
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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