^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * timers.c -- generic ColdFire hardware timer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/profile.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcftimer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * By default use timer1 as the system clock timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FREQ (MCF_BUSCLK / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TA(a) (MCFTIMER_BASE1 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * These provide the underlying interrupt vector support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Unfortunately it is a little different on each ColdFire.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void coldfire_profile_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define __raw_readtrr __raw_readl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define __raw_writetrr __raw_writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define __raw_readtrr __raw_readw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define __raw_writetrr __raw_writew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static u32 mcftmr_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static u32 mcftmr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static irq_handler_t timer_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static void init_timer_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef MCFSIM_ICR_AUTOVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Timer1 is always used as system timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MCFSIM_TIMER1ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mcf_mapirq2imr(MCF_IRQ_TIMER, MCFINTC_TIMER1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef CONFIG_HIGHPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Timer2 is to be used as a high speed profile timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MCFSIM_TIMER2ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mcf_mapirq2imr(MCF_IRQ_PROFILER, MCFINTC_TIMER2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* MCFSIM_ICR_AUTOVEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static irqreturn_t mcftmr_tick(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Reset the ColdFire timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, TA(MCFTIMER_TER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mcftmr_cnt += mcftmr_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) return timer_interrupt(irq, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static u64 mcftmr_read_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 tcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tcn = __raw_readw(TA(MCFTIMER_TCN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) cycles = mcftmr_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return cycles + tcn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static struct clocksource mcftmr_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "tmr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .read = mcftmr_read_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void hw_timer_init(irq_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __raw_writew(MCFTIMER_TMR_DISABLE, TA(MCFTIMER_TMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mcftmr_cycles_per_jiffy = FREQ / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * The coldfire timer runs from 0 to TRR included, then 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * again and so on. It counts thus actually TRR + 1 steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * for 1 tick, not TRR. So if you want n cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * initialize TRR with n - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __raw_writetrr(mcftmr_cycles_per_jiffy - 1, TA(MCFTIMER_TRR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, TA(MCFTIMER_TMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) clocksource_register_hz(&mcftmr_clk, FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) timer_interrupt = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) init_timer_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) r = request_irq(MCF_IRQ_TIMER, mcftmr_tick, IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ERR_PTR(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #ifdef CONFIG_HIGHPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) coldfire_profile_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #ifdef CONFIG_HIGHPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * By default use timer2 as the profiler clock timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PA(a) (MCFTIMER_BASE2 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * Choose a reasonably fast profile timer. Make it an odd value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * try and get good coverage of kernel operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PROFILEHZ 1013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Use the other timer to provide high accuracy profiling info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) irqreturn_t coldfire_profile_tick(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Reset ColdFire timer2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) __raw_writeb(MCFTIMER_TER_CAP | MCFTIMER_TER_REF, PA(MCFTIMER_TER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (current->pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) profile_tick(CPU_PROFILING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) void coldfire_profile_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) printk(KERN_INFO "PROFILE: lodging TIMER2 @ %dHz as profile timer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PROFILEHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Set up TIMER 2 as high speed profile clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __raw_writew(MCFTIMER_TMR_DISABLE, PA(MCFTIMER_TMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) __raw_writetrr(((MCF_BUSCLK / 16) / PROFILEHZ), PA(MCFTIMER_TRR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __raw_writew(MCFTIMER_TMR_ENORI | MCFTIMER_TMR_CLK16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENABLE, PA(MCFTIMER_TMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = request_irq(MCF_IRQ_PROFILER, coldfire_profile_tick, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "profile timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pr_err("Failed to request irq %d (profile timer): %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MCF_IRQ_PROFILER, ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #endif /* CONFIG_HIGHPROFILE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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