^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * stmark2.c -- Support for Sysam AMCORE open board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mtd/partitions.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi-fsl-dspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/spi/flash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Partitioning of parallel NOR flash (39VF3201B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static struct mtd_partition stmark2_partitions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .name = "U-Boot (1024K)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .size = 0x100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .offset = 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .name = "Kernel+initramfs (7168K)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .size = 0x700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .offset = MTDPART_OFS_APPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = "Flash Free Space (8192K)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .size = MTDPART_SIZ_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .offset = MTDPART_OFS_APPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static struct flash_platform_data stmark2_spi_flash_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .name = "is25lp128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .parts = stmark2_partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .nr_parts = ARRAY_SIZE(stmark2_partitions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .type = "is25lp128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct spi_board_info stmark2_board_info[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .modalias = "m25p80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .max_speed_hz = 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .chip_select = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .platform_data = &stmark2_spi_flash_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .mode = SPI_MODE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* SPI controller data, SPI (0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static struct fsl_dspi_platform_data dspi_spi0_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .cs_num = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .sck_cs_delay = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .cs_sck_delay = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct resource dspi_spi0_resource[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .start = MCFDSPI_BASE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .end = MCFDSPI_BASE0 + 0xFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .start = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .end = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .flags = IORESOURCE_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .start = MCF_IRQ_DSPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .end = MCF_IRQ_DSPI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static u64 stmark2_dspi_mask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* SPI controller, id = bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static struct platform_device dspi_spi0_device = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "fsl-dspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .num_resources = ARRAY_SIZE(dspi_spi0_resource),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .resource = dspi_spi0_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .platform_data = &dspi_spi0_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .dma_mask = &stmark2_dspi_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static struct platform_device *stmark2_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &dspi_spi0_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Note: proper pin-mux setup is mandatory for proper SPI functionality.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int __init init_stmark2(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* DSPI0, all pins as DSPI, and using CS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __raw_writeb(0xfc, MCFGPIO_PAR_DSPIOWH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Board gpio setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __raw_writeb(0x00, MCFGPIO_PAR_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_writeb(0x00, MCFGPIO_PAR_FBCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) __raw_writeb(0x00, MCFGPIO_PAR_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __raw_writeb(0x00, MCFGPIO_PAR_CANI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) platform_add_devices(stmark2_devices, ARRAY_SIZE(stmark2_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) spi_register_board_info(stmark2_board_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ARRAY_SIZE(stmark2_board_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) late_initcall(init_stmark2);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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