^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * sltimers.c -- generic ColdFire slice timer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * timers.c -- generic ColdFire hardware timer support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/profile.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mcfslt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_HIGHPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * By default use Slice Timer 1 as the profiler clock timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PA(a) (MCFSLT_TIMER1 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Choose a reasonably fast profile timer. Make it an odd value to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * try and get good coverage of kernel operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PROFILEHZ 1013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Reset Slice Timer 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (current->pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) profile_tick(CPU_PROFILING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) void mcfslt_profile_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PROFILEHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = request_irq(MCF_IRQ_PROFILER, mcfslt_profile_tick, IRQF_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "profile timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pr_err("Failed to request irq %d (profile timer): %pe\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MCF_IRQ_PROFILER, ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Set up TIMER 2 as high speed profile clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PA(MCFSLT_SCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif /* CONFIG_HIGHPROFILE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * By default use Slice Timer 0 as the system clock timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TA(a) (MCFSLT_TIMER0 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static u32 mcfslt_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static u32 mcfslt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static irq_handler_t timer_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static irqreturn_t mcfslt_tick(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Reset Slice Timer 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mcfslt_cnt += mcfslt_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return timer_interrupt(irq, dummy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static u64 mcfslt_read_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 cycles, scnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) scnt = __raw_readl(TA(MCFSLT_SCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) cycles = mcfslt_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (__raw_readl(TA(MCFSLT_SSR)) & MCFSLT_SSR_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cycles += mcfslt_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) scnt = __raw_readl(TA(MCFSLT_SCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* subtract because slice timers count down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return cycles + ((mcfslt_cycles_per_jiffy - 1) - scnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct clocksource mcfslt_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = "slt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .rating = 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .read = mcfslt_read_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) void hw_timer_init(irq_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The coldfire slice timer (SLT) runs from STCNT to 0 included,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * then STCNT again and so on. It counts thus actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * STCNT + 1 steps for 1 tick, not STCNT. So if you want
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * n cycles, initialize STCNT with n - 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TA(MCFSLT_SCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* initialize mcfslt_cnt knowing that slice timers count down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mcfslt_cnt = mcfslt_cycles_per_jiffy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) timer_interrupt = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) r = request_irq(MCF_IRQ_TIMER, mcfslt_tick, IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_TIMER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ERR_PTR(r));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clocksource_register_hz(&mcfslt_clk, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef CONFIG_HIGHPROFILE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mcfslt_profile_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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