Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * reset.c  -- common ColdFire SoC reset support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  *	There are 2 common methods amongst the ColdFure parts for reseting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  *	the CPU. But there are couple of exceptions, the 5272 and the 547x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  *	have something completely special to them, and we let their specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  *	subarch code handle them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifdef MCFSIM_SYPCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static void mcf_cpu_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	/* Set watchdog to soft reset, and enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	__raw_writeb(0xc0, MCFSIM_SYPCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		/* wait for watchdog to timeout */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifdef MCF_RCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static void mcf_cpu_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	__raw_writeb(MCF_RCR_SWRESET, MCF_RCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int __init mcf_setup_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	mach_reset = mcf_cpu_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) arch_initcall(mcf_setup_reset);