^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * pit.c -- Freescale ColdFire PIT timer. Currently this type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * hardware timer only exists in the Freescale ColdFire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * 5270/5271, 5282 and 5208 CPUs. No doubt newer ColdFire
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * family members will probably use it too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999-2008, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/clockchips.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mcfpit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * By default use timer1 as the system clock timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FREQ ((MCF_CLK / 2) / 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TA(a) (MCFPIT_BASE1 + (a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIT_CYCLES_PER_JIFFY (FREQ / HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u32 pit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Initialize the PIT timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * This is also called after resume to bring the PIT into operation again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int cf_pit_set_periodic(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __raw_writew(PIT_CYCLES_PER_JIFFY, TA(MCFPIT_PMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MCFPIT_PCSR_OVW | MCFPIT_PCSR_RLD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int cf_pit_set_oneshot(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MCFPIT_PCSR_OVW | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static int cf_pit_shutdown(struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Program the next event in oneshot mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Delta is given in PIT ticks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int cf_pit_next_event(unsigned long delta,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct clock_event_device *evt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) __raw_writew(delta, TA(MCFPIT_PMR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct clock_event_device cf_pit_clockevent = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .name = "pit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .features = CLOCK_EVT_FEAT_PERIODIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CLOCK_EVT_FEAT_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .set_state_shutdown = cf_pit_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .set_state_periodic = cf_pit_set_periodic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .set_state_oneshot = cf_pit_set_oneshot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .set_next_event = cf_pit_next_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .shift = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .irq = MCF_IRQ_PIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static irqreturn_t pit_tick(int irq, void *dummy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct clock_event_device *evt = &cf_pit_clockevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 pcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Reset the ColdFire timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) pcsr = __raw_readw(TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pit_cnt += PIT_CYCLES_PER_JIFFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) evt->event_handler(evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static u64 pit_read_clk(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 cycles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 pcntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pcntr = __raw_readw(TA(MCFPIT_PCNTR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) cycles = pit_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return cycles + PIT_CYCLES_PER_JIFFY - pcntr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static struct clocksource pit_clk = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .name = "pit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .rating = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .read = pit_read_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mask = CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) void hw_timer_init(irq_handler_t handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cf_pit_clockevent.cpumask = cpumask_of(smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cf_pit_clockevent.mult = div_sc(FREQ, NSEC_PER_SEC, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) cf_pit_clockevent.max_delta_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) clockevent_delta2ns(0xFFFF, &cf_pit_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) cf_pit_clockevent.max_delta_ticks = 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cf_pit_clockevent.min_delta_ns =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) clockevent_delta2ns(0x3f, &cf_pit_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cf_pit_clockevent.min_delta_ticks = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) clockevents_register_device(&cf_pit_clockevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ret = request_irq(MCF_IRQ_PIT1, pit_tick, IRQF_TIMER, "timer", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_err("Failed to request irq %d (timer): %pe\n", MCF_IRQ_PIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ERR_PTR(ret));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) clocksource_register_hz(&pit_clk, FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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