^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * pci.c -- PCI bus support for ColdFire processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/m54xxpci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Memory and IO mappings. We use a 1:1 mapping for local host memory to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * PCI bus memory (no reason not to really). IO space is mapped in its own
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * separate address region. The device configuration space is mapped over
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * the IO map space when we enable it in the PCICAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct pci_bus *rootbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static unsigned long iospace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * We need to be carefull probing on bus 0 (directly connected to host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * bridge). We should only access the well defined possible devices in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * use, ignore aliases and the like.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static unsigned char mcf_host_slot2sid[32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 0, 1, 2, 0, 3, 4, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static unsigned char mcf_host_irq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 0, 69, 69, 71, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Configuration space access functions. Configuration space access is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * through the IO mapping window, enabling it via the PCICAR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) int where, int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *value = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) addr = mcf_mk_pcicar(bus->number, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __raw_writel(PCICAR_E | addr, PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __raw_readl(PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) addr = iospace + (where & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) *value = __raw_readb(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *value = le16_to_cpu(__raw_readw(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *value = le32_to_cpu(__raw_readl(addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __raw_writel(0, PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __raw_readl(PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) int where, int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (bus->number == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (mcf_host_slot2sid[PCI_SLOT(devfn)] == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) addr = mcf_mk_pcicar(bus->number, devfn, where);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __raw_writel(PCICAR_E | addr, PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __raw_readl(PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) addr = iospace + (where & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __raw_writeb(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __raw_writew(cpu_to_le16(value), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) __raw_writel(cpu_to_le32(value), addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __raw_writel(0, PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __raw_readl(PCICAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static struct pci_ops mcf_pci_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .read = mcf_pci_readconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .write = mcf_pci_writeconfig,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * Initialize the PCI bus registers, and scan the bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct resource mcf_pci_mem = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "PCI Memory space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .start = PCI_MEM_PA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .end = PCI_MEM_PA + PCI_MEM_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static struct resource mcf_pci_io = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = "PCI IO space",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .start = 0x400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .end = 0x10000 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .flags = IORESOURCE_IO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static struct resource busn_resource = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .name = "PCI busn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .start = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .end = 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .flags = IORESOURCE_BUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Interrupt mapping and setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int mcf_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) sid = mcf_host_slot2sid[slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (sid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return mcf_host_irq[sid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int __init mcf_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pci_host_bridge *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bridge = pci_alloc_host_bridge(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (!bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pr_info("ColdFire: PCI bus initialization...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Reset the external PCI bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) __raw_writel(PCIGSCR_RESET, PCIGSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __raw_writel(0, PCITCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) request_resource(&iomem_resource, &mcf_pci_mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) request_resource(&iomem_resource, &mcf_pci_io);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Configure PCI arbiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PACR_EXTMINTE(0x1f), PACR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Set required multi-function pins for PCI bus use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Set up config space for local host bus controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PCI_COMMAND_INVALIDATE, PCISCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __raw_writel(0, PCICR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * Set up the initiator windows for memory and IO mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * These give the CPU bus access onto the PCI bus. One for each of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * PCI memory and IO address spaces.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PCIIW0BTAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PCIIW1BTAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Set up the target windows for access from the PCI bus back to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * CPU bus. All we need is access to system RAM (for mastering).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __raw_writel(CONFIG_RAMBASE, PCIBAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Keep a virtual mapping to IO/config space active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (iospace == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pci_free_host_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (u32) iospace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Turn of PCI reset, and wait for devices to settle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __raw_writel(0, PCIGSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) set_current_state(TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) schedule_timeout(msecs_to_jiffies(200));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pci_add_resource(&bridge->windows, &ioport_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pci_add_resource(&bridge->windows, &iomem_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pci_add_resource(&bridge->windows, &busn_resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bridge->dev.parent = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bridge->sysdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) bridge->busnr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bridge->ops = &mcf_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bridge->swizzle_irq = pci_common_swizzle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) bridge->map_irq = mcf_pci_map_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ret = pci_scan_root_bus_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) pci_free_host_bridge(bridge);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rootbus = bridge->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) rootbus->resource[0] = &mcf_pci_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rootbus->resource[1] = &mcf_pci_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pci_bus_size_bridges(rootbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pci_bus_assign_resources(rootbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pci_bus_add_devices(rootbus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) subsys_initcall(mcf_pci_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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