^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m54xx.c -- platform support for ColdFire 54xx based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/pgalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/m54xxsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/m54xxgpt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) &clk_mcfslt0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &clk_mcfslt1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &clk_mcfuart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) &clk_mcfuart3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __init m54xx_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* enable io pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MCFGPIO_PAR_PSC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void __init m54xx_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* set the fec/i2c/irq pin assignment register for i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) r = readl(MCF_PAR_FECI2CIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(r, MCF_PAR_FECI2CIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void mcf54xx_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* disable interrupts and enable the watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) asm("movew #0x2700, %sr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) __raw_writel(0, MCF_GPT_GMS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MCF_GPT_GMS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mach_reset = mcf54xx_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) m54xx_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) m54xx_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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