^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * m5441x.c -- support for Coldfire m5441x processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * (C) Copyright Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mcfdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_CLK(0, "edma", 17, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(0, "fsl-dspi.0", 23, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(0, "mcfuart.3", 27, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_CLK(0, "mcfadc.0", 38, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_CLK(0, "mcfdac.0", 39, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_CLK(0, "mcfsim.0", 43, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_CLK(0, "mcfddr-sram.0", 46, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_CLK(0, "mcfssi.0", 47, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_CLK(0, "mcfrng.0", 49, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_CLK(0, "mcfssi.1", 50, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_CLK(0, "sdhci-esdhc-mcf.0", 51, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_CLK(0, "enet-fec.0", 53, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_CLK(0, "enet-fec.1", 54, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_CLK(0, "switch.0", 55, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DEFINE_CLK(1, "mcfuart.7", 27, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DEFINE_CLK(1, "mcfuart.8", 28, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DEFINE_CLK(1, "mcfuart.9", 29, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEFINE_CLK(1, "mcfpwm.0", 34, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DEFINE_CLK(1, "sys.0", 36, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DEFINE_CLK(1, "gpio.0", 37, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) DEFINE_CLK(2, "ipg.0", 0, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) DEFINE_CLK(2, "ahb.0", 1, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DEFINE_CLK(2, "per.0", 2, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &__clk_0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &__clk_0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &__clk_0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) &__clk_0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &__clk_0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) &__clk_0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) &__clk_0_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &__clk_0_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) &__clk_0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &__clk_0_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &__clk_0_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &__clk_0_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &__clk_0_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &__clk_0_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &__clk_0_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) &__clk_0_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &__clk_0_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &__clk_0_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) &__clk_0_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &__clk_0_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &__clk_0_33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &__clk_0_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &__clk_0_35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &__clk_0_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) &__clk_0_38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) &__clk_0_39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) &__clk_0_42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) &__clk_0_43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &__clk_0_44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &__clk_0_45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &__clk_0_46,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &__clk_0_47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) &__clk_0_48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &__clk_0_49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &__clk_0_50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &__clk_0_51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &__clk_0_53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &__clk_0_54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &__clk_0_55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &__clk_0_56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &__clk_0_63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &__clk_1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &__clk_1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) &__clk_1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) &__clk_1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) &__clk_1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &__clk_1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &__clk_1_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &__clk_1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &__clk_1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &__clk_1_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) &__clk_1_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &__clk_1_34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &__clk_1_36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &__clk_1_37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &__clk_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &__clk_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &__clk_2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct clk * const enable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* make sure these clocks are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) &__clk_0_15, /* dspi.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) &__clk_0_17, /* eDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) &__clk_0_18, /* intc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) &__clk_0_19, /* intc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) &__clk_0_20, /* intc0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) &__clk_0_23, /* dspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) &__clk_0_24, /* uart0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) &__clk_0_25, /* uart1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) &__clk_0_26, /* uart2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &__clk_0_27, /* uart3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) &__clk_0_33, /* pit.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) &__clk_0_37, /* eport */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) &__clk_0_48, /* pll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) &__clk_0_51, /* esdhc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &__clk_1_36, /* CCM/reset module/Power management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) &__clk_1_37, /* gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct clk * const disable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) &__clk_0_8, /* can.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) &__clk_0_9, /* can.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) &__clk_0_14, /* i2c.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) &__clk_0_22, /* i2c.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) &__clk_0_23, /* dspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) &__clk_0_28, /* tmr.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) &__clk_0_29, /* tmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) &__clk_0_30, /* tmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) &__clk_0_31, /* tmr.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) &__clk_0_32, /* pit.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) &__clk_0_34, /* pit.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) &__clk_0_35, /* pit.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) &__clk_0_38, /* adc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &__clk_0_39, /* dac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &__clk_0_44, /* usb otg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &__clk_0_45, /* usb host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &__clk_0_47, /* ssi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &__clk_0_49, /* rng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &__clk_0_50, /* ssi.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &__clk_0_51, /* eSDHC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &__clk_0_53, /* enet-fec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &__clk_0_54, /* enet-fec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &__clk_0_55, /* switch.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &__clk_0_56, /* switch.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &__clk_1_2, /* 1-wire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &__clk_1_4, /* i2c.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &__clk_1_5, /* i2c.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &__clk_1_6, /* i2c.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &__clk_1_7, /* i2c.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &__clk_1_24, /* uart 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) &__clk_1_25, /* uart 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) &__clk_1_26, /* uart 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) &__clk_1_27, /* uart 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) &__clk_1_28, /* uart 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) &__clk_1_29, /* uart 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static void __clk_enable2(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) __raw_writel(__raw_readl(MCFSDHC_CLK) | (1 << clk->slot), MCFSDHC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static void __clk_disable2(struct clk *clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) __raw_writel(__raw_readl(MCFSDHC_CLK) & ~(1 << clk->slot), MCFSDHC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct clk_ops clk_ops2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .enable = __clk_enable2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .disable = __clk_disable2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void __init m5441x_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __clk_init_enabled(enable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* make sure these clocks are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) __clk_init_disabled(disable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static void __init m5441x_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) __raw_writeb(0x0f, MCFGPIO_PAR_UART0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __raw_writeb(0x00, MCFGPIO_PAR_UART1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __raw_writeb(0x00, MCFGPIO_PAR_UART2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void __init m5441x_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __raw_writeb(0x03, MCFGPIO_PAR_FEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) m5441x_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) m5441x_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) m5441x_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags