Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *	m5407.c  -- platform support for ColdFire 5407 based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *	Copyright (C) 2000, Lineo (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	&clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	&clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	&clk_mcftmr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	&clk_mcftmr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	&clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	&clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	&clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void __init m5407_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	       MCFSIM_I2CICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	/* Only support the external interrupts on their primary level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	mcf_mapirq2imr(25, MCFINTC_EINT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	mcf_mapirq2imr(27, MCFINTC_EINT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	mcf_mapirq2imr(29, MCFINTC_EINT5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	mcf_mapirq2imr(31, MCFINTC_EINT7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	m5407_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /***************************************************************************/