^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m53xx.c -- platform support for ColdFire 53xx based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2000, Lineo (www.lineo.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Yaroslav Vinogradov yaroslav.vinogradov@freescale.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright Freescale Semiconductor, Inc 2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 2006, emlix, Sebastian Hess <shess@hessware.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mcfdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mcfwdebug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(0, "edma", 17, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) &__clk_0_2, /* flexbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) &__clk_0_8, /* mcfcan.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) &__clk_0_12, /* fec.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &__clk_0_17, /* edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &__clk_0_18, /* intc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &__clk_0_19, /* intc.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &__clk_0_21, /* iack.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &__clk_0_22, /* imx1-i2c.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) &__clk_0_23, /* mcfqspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) &__clk_0_24, /* mcfuart.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) &__clk_0_25, /* mcfuart.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &__clk_0_26, /* mcfuart.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) &__clk_0_28, /* mcftmr.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &__clk_0_29, /* mcftmr.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &__clk_0_30, /* mcftmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &__clk_0_31, /* mcftmr.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &__clk_0_32, /* mcfpit.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) &__clk_0_33, /* mcfpit.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) &__clk_0_34, /* mcfpit.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &__clk_0_35, /* mcfpit.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) &__clk_0_36, /* mcfpwm.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &__clk_0_37, /* mcfeport.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &__clk_0_38, /* mcfwdt.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &__clk_0_40, /* sys.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) &__clk_0_41, /* gpio.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) &__clk_0_42, /* mcfrtc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &__clk_0_43, /* mcflcd.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) &__clk_0_44, /* mcfusb-otg.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &__clk_0_45, /* mcfusb-host.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &__clk_0_46, /* sdram.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) &__clk_0_47, /* ssi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &__clk_0_48, /* pll.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &__clk_1_32, /* mdha.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &__clk_1_33, /* skha.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &__clk_1_34, /* rng.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct clk * const enable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &__clk_0_2, /* flexbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) &__clk_0_18, /* intc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) &__clk_0_19, /* intc.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) &__clk_0_21, /* iack.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) &__clk_0_24, /* mcfuart.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) &__clk_0_25, /* mcfuart.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) &__clk_0_26, /* mcfuart.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) &__clk_0_28, /* mcftmr.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) &__clk_0_29, /* mcftmr.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) &__clk_0_32, /* mcfpit.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &__clk_0_33, /* mcfpit.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) &__clk_0_37, /* mcfeport.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) &__clk_0_40, /* sys.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) &__clk_0_41, /* gpio.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) &__clk_0_46, /* sdram.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &__clk_0_48, /* pll.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static struct clk * const disable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) &__clk_0_8, /* mcfcan.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) &__clk_0_12, /* fec.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) &__clk_0_17, /* edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) &__clk_0_22, /* imx1-i2c.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) &__clk_0_23, /* mcfqspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) &__clk_0_30, /* mcftmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) &__clk_0_31, /* mcftmr.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) &__clk_0_34, /* mcfpit.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) &__clk_0_35, /* mcfpit.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) &__clk_0_36, /* mcfpwm.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) &__clk_0_38, /* mcfwdt.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) &__clk_0_42, /* mcfrtc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) &__clk_0_43, /* mcflcd.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) &__clk_0_44, /* mcfusb-otg.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) &__clk_0_45, /* mcfusb-host.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) &__clk_0_47, /* ssi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) &__clk_1_32, /* mdha.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) &__clk_1_33, /* skha.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) &__clk_1_34, /* rng.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void __init m53xx_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* make sure these clocks are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) __clk_init_enabled(enable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* make sure these clocks are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) __clk_init_disabled(disable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void __init m53xx_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* setup QSPS pins for QSPI with gpio CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writew(0x01f0, MCFGPIO_PAR_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void __init m53xx_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* setup Port AS Pin Assignment Register for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* set PASPA0 to SCL and PASPA1 to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 r = readb(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) r |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writeb(r, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void __init m53xx_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* UART GPIO initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writew(readw(MCFGPIO_PAR_UART) | 0x0FFF, MCFGPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void __init m53xx_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Set multi-function pins to ethernet mode for fec0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) v = readb(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) v |= MCF_GPIO_PAR_FECI2C_PAR_MDC_EMDC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MCF_GPIO_PAR_FECI2C_PAR_MDIO_EMDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writeb(v, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) v = readb(MCFGPIO_PAR_FEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) v = MCF_GPIO_PAR_FEC_PAR_FEC_7W_FEC | MCF_GPIO_PAR_FEC_PAR_FEC_MII_FEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) writeb(v, MCFGPIO_PAR_FEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if !defined(CONFIG_BOOTPARAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Copy command line from FLASH to local buffer... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) memcpy(commandp, (char *) 0x4000, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if(strncmp(commandp, "kcl ", 4) == 0){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) memcpy(commandp, (char *) 0x4004, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) commandp[size-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) memset(commandp, 0, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) m53xx_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) m53xx_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) m53xx_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) m53xx_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) m53xx_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_BDM_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * Disable the BDM clocking. This also turns off most of the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * the BDM device. This is good for EMC reasons. This option is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * incompatible with the memory protection option.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Board initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * PLL min/max specifications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MAX_FVCO 500000 /* KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MAX_FSYS 80000 /* KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MIN_FSYS 58333 /* KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define FREF 16000 /* KHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MAX_MFD 135 /* Multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MIN_MFD 88 /* Multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BUSDIV 6 /* Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Low Power Divider specifications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MIN_LPD (1 << 0) /* Divider (not encoded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MAX_LPD (1 << 15) /* Divider (not encoded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SYS_CLK_KHZ 80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SYSTEM_PERIOD 12.5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * SDRAM Timing Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SDRAM_BL 8 /* # of beats in a burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SDRAM_TWR 2 /* in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SDRAM_CASL 2.5 /* CASL in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SDRAM_TRCD 2 /* in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SDRAM_TRP 2 /* in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SDRAM_TRFC 7 /* in clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SDRAM_TREFI 7800 /* in ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define EXT_SRAM_ADDRESS (0xC0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define FLASH_ADDRESS (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SDRAM_ADDRESS (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define NAND_FLASH_ADDRESS (0xD0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) void wtm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void scm_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) void gpio_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void fbcs_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) void sdramc_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int clock_pll (int fsys, int flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int clock_limp (int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int clock_exit_limp (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int get_sys_clock (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) asmlinkage void __init sysinit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) clock_pll(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) wtm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) scm_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) gpio_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) fbcs_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) sdramc_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) void wtm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* Disable watchdog timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) writew(0, MCF_WTM_WCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MCF_SCM_BCR_GBW (0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MCF_SCM_BCR_GBR (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void scm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* All masters are trusted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writel(0x77777777, MCF_SCM_MPR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* Allow supervisor/user, read/write, and trusted/untrusted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) access to all slaves */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writel(0, MCF_SCM_PACRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) writel(0, MCF_SCM_PACRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) writel(0, MCF_SCM_PACRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) writel(0, MCF_SCM_PACRD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) writel(0, MCF_SCM_PACRE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) writel(0, MCF_SCM_PACRF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Enable bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) void fbcs_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) writeb(0x3E, MCFGPIO_PAR_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Latch chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(0x10080000, MCF_FBCS1_CSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) writel(0x002A3780, MCF_FBCS1_CSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Initialize latch to drive signals to inactive states */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writew(0xffff, 0x10080000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* External SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) writel(MCF_FBCS_CSCR_PS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MCF_FBCS_CSCR_AA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) MCF_FBCS_CSCR_SBM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) MCF_FBCS_CSCR_WS(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MCF_FBCS1_CSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Boot Flash connected to FBCS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) writel(FLASH_ADDRESS, MCF_FBCS0_CSAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) writel(MCF_FBCS_CSCR_PS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MCF_FBCS_CSCR_BEM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MCF_FBCS_CSCR_AA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MCF_FBCS_CSCR_SBM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MCF_FBCS_CSCR_WS(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MCF_FBCS0_CSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) void sdramc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Check to see if the SDRAM has already been initialized
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * by a run control tool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (!(readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* SDRAM chip select initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Initialize SDRAM chip select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MCF_SDRAMC_SDCS_CSSZ(MCF_SDRAMC_SDCS_CSSZ_32MBYTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MCF_SDRAMC_SDCS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * Basic configuration and initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MCF_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MCF_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL * 2) + 2)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MCF_SDRAMC_SDCFG1_ACT2RW((int)(SDRAM_TRCD + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MCF_SDRAMC_SDCFG1_PRE2ACT((int)(SDRAM_TRP + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MCF_SDRAMC_SDCFG1_REF2ACT((int)(SDRAM_TRFC + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MCF_SDRAMC_SDCFG1_WTLAT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MCF_SDRAMC_SDCFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MCF_SDRAMC_SDCFG2_BWT2RW(SDRAM_BL / 2 + SDRAM_TWR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MCF_SDRAMC_SDCFG2_BRD2WT((int)((SDRAM_CASL + SDRAM_BL / 2 - 1.0) + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MCF_SDRAMC_SDCFG2_BL(SDRAM_BL - 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MCF_SDRAMC_SDCFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Precharge and enable write to SDMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) writel(MCF_SDRAMC_SDCR_MODE_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MCF_SDRAMC_SDCR_CKE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MCF_SDRAMC_SDCR_DDR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MCF_SDRAMC_SDCR_MUX(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MCF_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI / (SYSTEM_PERIOD * 64)) - 1) + 0.5)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MCF_SDRAMC_SDCR_PS_16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MCF_SDRAMC_SDCR_IPALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Write extended mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) writel(MCF_SDRAMC_SDMR_BNKAD_LEMR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MCF_SDRAMC_SDMR_AD(0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MCF_SDRAMC_SDMR_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MCF_SDRAMC_SDMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Write mode register and reset DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MCF_SDRAMC_SDMR_AD(0x163) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MCF_SDRAMC_SDMR_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MCF_SDRAMC_SDMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * Execute a PALL command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Perform two REF cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Write mode register and clear reset DLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) writel(MCF_SDRAMC_SDMR_BNKAD_LMR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MCF_SDRAMC_SDMR_AD(0x063) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MCF_SDRAMC_SDMR_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MCF_SDRAMC_SDMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Enable auto refresh and lock SDMR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) void gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Enable UART0 pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) writew(MCF_GPIO_PAR_UART_PAR_URXD0 | MCF_GPIO_PAR_UART_PAR_UTXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MCFGPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * Initialize TIN3 as a GPIO output to enable the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * half of the latch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) writeb(0x00, MCFGPIO_PAR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) writeb(0x08, MCFGPIO_PDDR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) writeb(0x00, MCFGPIO_PCLRR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int clock_pll(int fsys, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int fref, temp, fout, mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) fref = FREF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (fsys == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Return current PLL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) mfd = readb(MCF_PLL_PFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return (fref * mfd / (BUSDIV * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Check bounds of requested system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (fsys > MAX_FSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fsys = MAX_FSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (fsys < MIN_FSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fsys = MIN_FSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Multiplying by 100 when calculating the temp value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) and then dividing by 100 to calculate the mfd allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) for exact values without needing to include floating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) point libraries. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) temp = 100 * fsys / fref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) mfd = 4 * BUSDIV * temp / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Determine the output frequency for selected values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) fout = (fref * mfd / (BUSDIV * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Check to see if the SDRAM has already been initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * If it has then the SDRAM needs to be put into self refresh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * mode before reprogramming the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Put SDRAM into self refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Initialize the PLL to generate the new system clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * The device must be put into LIMP mode to reprogram the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Enter LIMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) clock_limp(DEFAULT_LPD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Reprogram PLL for desired fsys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) writeb(MCF_PLL_PODR_CPUDIV(BUSDIV/3) | MCF_PLL_PODR_BUSDIV(BUSDIV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MCF_PLL_PODR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) writeb(mfd, MCF_PLL_PFDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* Exit LIMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) clock_exit_limp();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * Return the SDRAM to normal operation if it is in use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (readl(MCF_SDRAMC_SDCR) & MCF_SDRAMC_SDCR_REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Exit self refresh mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MCF_SDRAMC_SDCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Errata - workaround for SDRAM opeartion after exiting LIMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* wait for DQS logic to relock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) for (i = 0; i < 0x200; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int clock_limp(int div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Check bounds of divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (div < MIN_LPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) div = MIN_LPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (div > MAX_LPD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) div = MAX_LPD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* Save of the current value of the SSIDIV so we don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) overwrite the value*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) temp = readw(MCF_CCM_CDR) & MCF_CCM_CDR_SSIDIV(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Apply the divider to the system clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writew(MCF_CCM_CDR_LPDIV(div) | MCF_CCM_CDR_SSIDIV(temp), MCF_CCM_CDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) writew(readw(MCF_CCM_MISCCR) | MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return (FREF/(3*(1 << div)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int clock_exit_limp(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Exit LIMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) writew(readw(MCF_CCM_MISCCR) & ~MCF_CCM_MISCCR_LIMP, MCF_CCM_MISCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Wait for PLL to lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) while (!(readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_PLL_LOCK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) fout = get_sys_clock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return fout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int get_sys_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int divider;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Test to see if device is in LIMP mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (readw(MCF_CCM_MISCCR) & MCF_CCM_MISCCR_LIMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) divider = readw(MCF_CCM_CDR) & MCF_CCM_CDR_LPDIV(0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return (FREF/(2 << divider));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return (FREF * readb(MCF_PLL_PFDR)) / (BUSDIV * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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