^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m527x.c -- platform support for ColdFire 527x based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sub-architcture dependent initialization code for the Freescale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 5270/5271 and 5274/5275 CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999-2004, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) &clk_mcfpit0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) &clk_mcfpit1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &clk_mcfpit2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) &clk_mcfpit3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) &clk_mcfuart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &clk_mcfqspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) &clk_fec0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) &clk_fec1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) &clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void __init m527x_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #if defined(CONFIG_M5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* setup QSPS pins for QSPI with gpio CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writeb(0x1f, MCFGPIO_PAR_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* and CS2 & CS3 as gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) par = readw(MCFGPIO_PAR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) par &= 0x3f3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) writew(par, MCFGPIO_PAR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #elif defined(CONFIG_M5275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* setup QSPS pins for QSPI with gpio CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writew(0x003e, MCFGPIO_PAR_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static void __init m527x_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #if defined(CONFIG_M5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u8 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* setup Port FECI2C Pin Assignment Register for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* set PAR_SCL to SCL and PAR_SDA to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) par = readb(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) par |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(par, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #elif defined(CONFIG_M5275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* setup Port FECI2C Pin Assignment Register for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* set PAR_SCL to SCL and PAR_SDA to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) par = readw(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) par |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) writew(par, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void __init m527x_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 sepmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * External Pin Mask Setting & Enable External Pin for Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sepmask = readw(MCFGPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) sepmask |= UART0_ENABLE_MASK | UART1_ENABLE_MASK | UART2_ENABLE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) writew(sepmask, MCFGPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static void __init m527x_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Set multi-function pins to ethernet mode for fec0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #if defined(CONFIG_M5271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) v = readb(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) writeb(v | 0xf0, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) par = readw(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writew(par | 0xf00, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) v = readb(MCFGPIO_PAR_FEC0HL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writeb(v | 0xc0, MCFGPIO_PAR_FEC0HL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Set multi-function pins to ethernet mode for fec1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) par = readw(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) writew(par | 0xa0, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) v = readb(MCFGPIO_PAR_FEC1HL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) writeb(v | 0xc0, MCFGPIO_PAR_FEC1HL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) m527x_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) m527x_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) m527x_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) m527x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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