^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m5272.c -- platform support for ColdFire 5272 based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001-2002, SnapGear Inc. (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/phy_fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Some platforms need software versions of the GPIO data registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) unsigned short ppdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned char ledbank = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(mcftmr2, "mcftmr.2", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(mcftmr3, "mcftmr.3", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) &clk_mcftmr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &clk_mcftmr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) &clk_mcftmr2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &clk_mcftmr3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) &clk_mcfqspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) &clk_fec0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static void __init m5272_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Enable the output lines for the serial ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) v = readl(MCFSIM_PBCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) v = (v & ~0x000000ff) | 0x00000055;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel(v, MCFSIM_PBCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) v = readl(MCFSIM_PDCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) v = (v & ~0x000003fc) | 0x000002a8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) writel(v, MCFSIM_PDCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void m5272_cpu_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Set watchdog to reset, and enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __raw_writew(0, MCFSIM_WIRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __raw_writew(1, MCFSIM_WRRR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __raw_writew(0, MCFSIM_WCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) for (;;)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* wait for watchdog to timeout */;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #if defined (CONFIG_MOD5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Set base of device vectors to be 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writeb(0x40, MCFSIM_PIVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #if defined(CONFIG_NETtel) || defined(CONFIG_SCALES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Copy command line from FLASH to local buffer... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) memcpy(commandp, (char *) 0xf0004000, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) commandp[size-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #elif defined(CONFIG_CANCam)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Copy command line from FLASH to local buffer... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) memcpy(commandp, (char *) 0xf0010000, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) commandp[size-1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) mach_reset = m5272_cpu_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Some 5272 based boards have the FEC ethernet directly connected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * an ethernet switch. In this case we need to use the fixed phy type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * and we need to declare it early in boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .link = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .speed = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .duplex = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int __init init_BSP(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) m5272_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) arch_initcall(init_BSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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