^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * 525x.c -- platform support for ColdFire 525x based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012, Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) &clk_mcftmr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) &clk_mcftmr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) &clk_mcfqspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) &clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &clk_mcfi2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static void __init m525x_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* set the GPIO function for the qspi cs gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* FIXME: replace with pinmux/pinctl support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 f = readl(MCFSIM2_GPIOFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) f |= (1 << MCFQSPI_CS2) | (1 << MCFQSPI_CS1) | (1 << MCFQSPI_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) writel(f, MCFSIM2_GPIOFUNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* QSPI irq setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MCFSIM_QSPIICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void __init m525x_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* first I2C controller uses regular irq setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MCFSIM_I2CICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* second I2C controller is completely different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) m525x_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) m525x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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