^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m5249.c -- platform support for ColdFire 5249 based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2002, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) &clk_mcftmr0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) &clk_mcftmr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) &clk_mcfqspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) &clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &clk_mcfi2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #ifdef CONFIG_M5249C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static struct resource m5249_smc91x_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .start = 0xe0000300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .end = 0xe0000300 + 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .start = MCF_IRQ_GPIO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .end = MCF_IRQ_GPIO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static struct platform_device m5249_smc91x = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = "smc91x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .num_resources = ARRAY_SIZE(m5249_smc91x_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .resource = m5249_smc91x_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif /* CONFIG_M5249C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static struct platform_device *m5249_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_M5249C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &m5249_smc91x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void __init m5249_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* QSPI irq setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL4 | MCFSIM_ICR_PRI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MCFSIM_QSPIICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mcf_mapirq2imr(MCF_IRQ_QSPI, MCFINTC_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void __init m5249_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* first I2C controller uses regular irq setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MCFSIM_I2CICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* second I2C controller is completely different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif /* CONFIG_I2C_IMX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #ifdef CONFIG_M5249C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void __init m5249_smc91x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Set the GPIO line as interrupt source for smc91x device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) gpio = readl(MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) writel(gpio | 0x40, MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) gpio = readl(MCFINTC2_INTPRI5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(gpio | 0x04000000, MCFINTC2_INTPRI5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #endif /* CONFIG_M5249C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #ifdef CONFIG_M5249C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) m5249_smc91x_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) m5249_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) m5249_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int __init init_BSP(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) platform_add_devices(m5249_devices, ARRAY_SIZE(m5249_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) arch_initcall(init_BSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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