^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m523x.c -- platform support for ColdFire 523x based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sub-architcture dependent initialization code for the Freescale
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * 523x CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1999-2005, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(pll, "pll.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(mcfpit0, "mcfpit.0", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(mcfpit1, "mcfpit.1", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(mcfpit2, "mcfpit.2", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(mcfpit3, "mcfpit.3", MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) &clk_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) &clk_sys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) &clk_mcfpit0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) &clk_mcfpit1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) &clk_mcfpit2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) &clk_mcfpit3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) &clk_mcfuart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) &clk_mcfuart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) &clk_mcfuart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) &clk_mcfqspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) &clk_fec0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &clk_mcfi2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static void __init m523x_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* setup QSPS pins for QSPI with gpio CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) writeb(0x1f, MCFGPIO_PAR_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* and CS2 & CS3 as gpio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) par = readw(MCFGPIO_PAR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) par &= 0x3f3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writew(par, MCFGPIO_PAR_TIMER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void __init m523x_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* setup Port AS Pin Assignment Register for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* set PASPA0 to SCL and PASPA1 to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) par = readb(MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) par |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writeb(par, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void __init m523x_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Set multi-function pins to ethernet use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(readb(MCFGPIO_PAR_FECI2C) | 0xf0, MCFGPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) m523x_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) m523x_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) m523x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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