^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * m520x.c -- platform support for ColdFire 520x based boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005, Freescale (www.freescale.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005, Intec Automation (mike@steroidmicros.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999-2007, Greg Ungerer (gerg@snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2001-2003, SnapGear Inc. (www.snapgear.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/param.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/mcfclk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) DEFINE_CLK(0, "edma", 17, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEFINE_CLK(0, "mcfeport.0", 34, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) DEFINE_CLK(0, "mcfwdt.0", 35, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) DEFINE_CLK(0, "pll.0", 36, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DEFINE_CLK(0, "sdram.0", 42, MCF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct clk *mcf_clks[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) &__clk_0_2, /* flexbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) &__clk_0_12, /* fec.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) &__clk_0_17, /* edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) &__clk_0_18, /* intc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) &__clk_0_21, /* iack.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) &__clk_0_22, /* imx1-i2c.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) &__clk_0_23, /* mcfqspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) &__clk_0_24, /* mcfuart.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) &__clk_0_25, /* mcfuart.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) &__clk_0_26, /* mcfuart.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) &__clk_0_28, /* mcftmr.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) &__clk_0_29, /* mcftmr.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) &__clk_0_30, /* mcftmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) &__clk_0_31, /* mcftmr.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) &__clk_0_32, /* mcfpit.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) &__clk_0_33, /* mcfpit.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) &__clk_0_34, /* mcfeport.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) &__clk_0_35, /* mcfwdt.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) &__clk_0_36, /* pll.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &__clk_0_40, /* sys.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &__clk_0_41, /* gpio.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &__clk_0_42, /* sdram.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct clk * const enable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) &__clk_0_2, /* flexbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &__clk_0_18, /* intc.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) &__clk_0_21, /* iack.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &__clk_0_24, /* mcfuart.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) &__clk_0_25, /* mcfuart.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) &__clk_0_26, /* mcfuart.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) &__clk_0_32, /* mcfpit.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) &__clk_0_33, /* mcfpit.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) &__clk_0_34, /* mcfeport.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &__clk_0_36, /* pll.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) &__clk_0_40, /* sys.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) &__clk_0_41, /* gpio.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) &__clk_0_42, /* sdram.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static struct clk * const disable_clks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) &__clk_0_12, /* fec.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) &__clk_0_17, /* edma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) &__clk_0_22, /* imx1-i2c.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) &__clk_0_23, /* mcfqspi.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) &__clk_0_28, /* mcftmr.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) &__clk_0_29, /* mcftmr.1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) &__clk_0_30, /* mcftmr.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) &__clk_0_31, /* mcftmr.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) &__clk_0_35, /* mcfwdt.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static void __init m520x_clk_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* make sure these clocks are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) for (i = 0; i < ARRAY_SIZE(enable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __clk_init_enabled(enable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* make sure these clocks are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (i = 0; i < ARRAY_SIZE(disable_clks); ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __clk_init_disabled(disable_clks[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void __init m520x_qspi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* setup Port QS for QSPI with gpio CS control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) writeb(0x3f, MCF_GPIO_PAR_QSPI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* make U1CTS and U2RTS gpio for cs_control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) par = readw(MCF_GPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) par &= 0x00ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writew(par, MCF_GPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void __init m520x_i2c_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* setup Port FECI2C Pin Assignment Register for I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* set PAR_SCL to SCL and PAR_SDA to SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) par = readb(MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) par |= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writeb(par, MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static void __init m520x_uarts_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 par2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* UART0 and UART1 GPIO pin setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) par = readw(MCF_GPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) par |= MCF_GPIO_PAR_UART_PAR_UTXD0 | MCF_GPIO_PAR_UART_PAR_URXD0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) par |= MCF_GPIO_PAR_UART_PAR_UTXD1 | MCF_GPIO_PAR_UART_PAR_URXD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) writew(par, MCF_GPIO_PAR_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* UART1 GPIO pin setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) par2 = readb(MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) par2 &= ~0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) par2 |= MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writeb(par2, MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static void __init m520x_fec_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Set multi-function pins to ethernet mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) v = readb(MCF_GPIO_PAR_FEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) writeb(v | 0xf0, MCF_GPIO_PAR_FEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) v = readb(MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) writeb(v | 0x0f, MCF_GPIO_PAR_FECI2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) void __init config_BSP(char *commandp, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) m520x_clk_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) m520x_uarts_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) m520x_fec_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) m520x_qspi_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) m520x_i2c_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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