^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * intc-simr.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * The EDGE Port interrupts are the fixed 7 external interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * They need some special treatment, for example they need to be acked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef CONFIG_M520x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The 520x parts only support a limited range of these external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * interrupts, only 1, 4 and 7 (as interrupts 65, 66 and 67).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EINT0 64 /* Is not actually used, but spot reserved for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EINT1 65 /* EDGE Port interrupt 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EINT4 66 /* EDGE Port interrupt 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EINT7 67 /* EDGE Port interrupt 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static unsigned int irqebitmap[] = { 0, 1, 4, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static inline unsigned int irq2ebit(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return irqebitmap[irq - EINT0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Most of the ColdFire parts with the EDGE Port module just have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * a strait direct mapping of the 7 external interrupts. Although
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * there is a bit reserved for 0, it is not used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EINT0 64 /* Is not actually used, but spot reserved for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EINT1 65 /* EDGE Port interrupt 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EINT7 71 /* EDGE Port interrupt 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline unsigned int irq2ebit(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return irq - EINT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * There maybe one, two or three interrupt control units, each has 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * interrupts. If there is no second or third unit then MCFINTC1_* or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * MCFINTC2_* defines will be 0 (and code for them optimized away).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static void intc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int irq = d->irq - MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (MCFINTC2_SIMR && (irq > 128))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __raw_writeb(irq - 128, MCFINTC2_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) else if (MCFINTC1_SIMR && (irq > 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) __raw_writeb(irq - 64, MCFINTC1_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) __raw_writeb(irq, MCFINTC0_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static void intc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned int irq = d->irq - MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (MCFINTC2_CIMR && (irq > 128))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) __raw_writeb(irq - 128, MCFINTC2_CIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) else if (MCFINTC1_CIMR && (irq > 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __raw_writeb(irq - 64, MCFINTC1_CIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __raw_writeb(irq, MCFINTC0_CIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void intc_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned int ebit = irq2ebit(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) __raw_writeb(0x1 << ebit, MCFEPORT_EPFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static unsigned int intc_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) if ((irq >= EINT1) && (irq <= EINT7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int ebit = irq2ebit(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #if defined(MCFEPORT_EPDDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Set EPORT line as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) v = __raw_readb(MCFEPORT_EPDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __raw_writeb(v & ~(0x1 << ebit), MCFEPORT_EPDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Set EPORT line as interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) v = __raw_readb(MCFEPORT_EPIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __raw_writeb(v | (0x1 << ebit), MCFEPORT_EPIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) irq -= MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (MCFINTC2_ICR0 && (irq > 128))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __raw_writeb(5, MCFINTC2_ICR0 + irq - 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) else if (MCFINTC1_ICR0 && (irq > 64))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __raw_writeb(5, MCFINTC1_ICR0 + irq - 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) __raw_writeb(5, MCFINTC0_ICR0 + irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) intc_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int intc_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int ebit, irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 pa, tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tb = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) tb = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tb = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Level triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) tb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) irq_set_handler(irq, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ebit = irq2ebit(irq) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) pa = __raw_readw(MCFEPORT_EPPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pa = (pa & ~(0x3 << ebit)) | (tb << ebit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __raw_writew(pa, MCFEPORT_EPPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static struct irq_chip intc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .name = "CF-INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .irq_startup = intc_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .irq_mask = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .irq_unmask = intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static struct irq_chip intc_irq_chip_edge_port = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .name = "CF-INTC-EP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .irq_startup = intc_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .irq_mask = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .irq_unmask = intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .irq_ack = intc_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .irq_set_type = intc_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int irq, eirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Mask all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) __raw_writeb(0xff, MCFINTC0_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (MCFINTC1_SIMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) __raw_writeb(0xff, MCFINTC1_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (MCFINTC2_SIMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __raw_writeb(0xff, MCFINTC2_SIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (MCFINTC2_ICR0 ? 64 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if ((irq >= EINT1) && (irq <= EINT7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) irq_set_chip(irq, &intc_irq_chip_edge_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) irq_set_chip(irq, &intc_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) irq_set_handler(irq, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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