^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * intc.c -- interrupt controller or ColdFire 5272 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel_stat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The 5272 ColdFire interrupt controller is nothing like any other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ColdFire interrupt controller - it truly is completely different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Given its age it is unlikely to be used on any other ColdFire CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The masking and priproty setting of interrupts on the 5272 is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * loose mapping of vector number to register and internal bits, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * a table is the easiest and quickest way to map them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Note that the external interrupts are edge triggered (unlike the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * internal interrupt sources which are level triggered). Which means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * they also need acknowledging via acknowledge bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct irqmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int icr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned char index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned char ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*MCF_IRQ_SPURIOUS*/ { .icr = 0, .index = 0, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*MCF_IRQ_EINT1*/ { .icr = MCFSIM_ICR1, .index = 28, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*MCF_IRQ_EINT2*/ { .icr = MCFSIM_ICR1, .index = 24, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*MCF_IRQ_EINT3*/ { .icr = MCFSIM_ICR1, .index = 20, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*MCF_IRQ_EINT4*/ { .icr = MCFSIM_ICR1, .index = 16, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /*MCF_IRQ_TIMER1*/ { .icr = MCFSIM_ICR1, .index = 12, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*MCF_IRQ_TIMER2*/ { .icr = MCFSIM_ICR1, .index = 8, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /*MCF_IRQ_TIMER3*/ { .icr = MCFSIM_ICR1, .index = 4, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*MCF_IRQ_TIMER4*/ { .icr = MCFSIM_ICR1, .index = 0, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*MCF_IRQ_UART1*/ { .icr = MCFSIM_ICR2, .index = 28, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*MCF_IRQ_UART2*/ { .icr = MCFSIM_ICR2, .index = 24, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*MCF_IRQ_PLIP*/ { .icr = MCFSIM_ICR2, .index = 20, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*MCF_IRQ_PLIA*/ { .icr = MCFSIM_ICR2, .index = 16, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*MCF_IRQ_USB0*/ { .icr = MCFSIM_ICR2, .index = 12, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*MCF_IRQ_USB1*/ { .icr = MCFSIM_ICR2, .index = 8, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*MCF_IRQ_USB2*/ { .icr = MCFSIM_ICR2, .index = 4, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*MCF_IRQ_USB3*/ { .icr = MCFSIM_ICR2, .index = 0, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*MCF_IRQ_USB4*/ { .icr = MCFSIM_ICR3, .index = 28, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /*MCF_IRQ_USB5*/ { .icr = MCFSIM_ICR3, .index = 24, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*MCF_IRQ_USB6*/ { .icr = MCFSIM_ICR3, .index = 20, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*MCF_IRQ_USB7*/ { .icr = MCFSIM_ICR3, .index = 16, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*MCF_IRQ_DMA*/ { .icr = MCFSIM_ICR3, .index = 12, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*MCF_IRQ_ERX*/ { .icr = MCFSIM_ICR3, .index = 8, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*MCF_IRQ_ETX*/ { .icr = MCFSIM_ICR3, .index = 4, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /*MCF_IRQ_ENTC*/ { .icr = MCFSIM_ICR3, .index = 0, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*MCF_IRQ_QSPI*/ { .icr = MCFSIM_ICR4, .index = 28, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /*MCF_IRQ_EINT5*/ { .icr = MCFSIM_ICR4, .index = 24, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*MCF_IRQ_EINT6*/ { .icr = MCFSIM_ICR4, .index = 20, .ack = 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * The act of masking the interrupt also has a side effect of 'ack'ing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * an interrupt on this irq (for the external irqs). So this mask function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * is also an ack_mask function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static void intc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) irq -= MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) v = 0x8 << intc_irqmap[irq].index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) writel(v, intc_irqmap[irq].icr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static void intc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) irq -= MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) v = 0xd << intc_irqmap[irq].index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) writel(v, intc_irqmap[irq].icr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void intc_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Only external interrupts are acked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) irq -= MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (intc_irqmap[irq].ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) v = readl(intc_irqmap[irq].icr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) v &= (0x7 << intc_irqmap[irq].index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) v |= (0x8 << intc_irqmap[irq].index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) writel(v, intc_irqmap[irq].icr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int intc_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) irq -= MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (intc_irqmap[irq].ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) v = readl(MCFSIM_PITR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (type == IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) v &= ~(0x1 << (32 - irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) v |= (0x1 << (32 - irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) writel(v, MCFSIM_PITR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Simple flow handler to deal with the external edge triggered interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * We need to be careful with the masking/acking due to the side effects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * of masking an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static void intc_external_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) handle_simple_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static struct irq_chip intc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "CF-INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .irq_mask = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .irq_unmask = intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .irq_mask_ack = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .irq_ack = intc_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .irq_set_type = intc_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int irq, edge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Mask all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) writel(0x88888888, MCFSIM_ICR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) writel(0x88888888, MCFSIM_ICR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) writel(0x88888888, MCFSIM_ICR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) writel(0x88888888, MCFSIM_ICR4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) for (irq = 0; (irq < NR_IRQS); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) irq_set_chip(irq, &intc_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) edge = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (edge) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) irq_set_handler(irq, intc_external_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) irq_set_handler(irq, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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