Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * intc2.c  -- support for the 2nd INTC controller of the 525x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * (C) Copyright 2012, Steven King <sfking@fdwdc.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static void intc2_irq_gpio_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32 imr = readl(MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	int irq = d->irq - MCF_IRQ_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		imr &= ~(0x001 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		imr &= ~(0x100 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	writel(imr, MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static void intc2_irq_gpio_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 imr = readl(MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	int irq = d->irq - MCF_IRQ_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		imr |= (0x001 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		imr |= (0x100 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	writel(imr, MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void intc2_irq_gpio_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u32 imr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u32 type = irqd_get_trigger_type(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	int irq = d->irq - MCF_IRQ_GPIO0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	if (type & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		imr |= (0x001 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	if (type & IRQ_TYPE_EDGE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		imr |= (0x100 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	writel(imr, MCFSIM2_GPIOINTCLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int intc2_irq_gpio_set_type(struct irq_data *d, unsigned int f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	if (f & ~IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static struct irq_chip intc2_irq_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	.name		= "CF-INTC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	.irq_mask	= intc2_irq_gpio_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	.irq_unmask	= intc2_irq_gpio_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	.irq_ack	= intc2_irq_gpio_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	.irq_set_type	= intc2_irq_gpio_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static int __init mcf_intc2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	/* set the interrupt base for the second interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	/* GPIO interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO6); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 		irq_set_chip(irq, &intc2_irq_gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 		irq_set_handler(irq, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) arch_initcall(mcf_intc2_init);