Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * intc2.c  -- support for the 2nd INTC controller of the 5249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * License.  See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static void intc2_irq_gpio_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	imr = readl(MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	imr &= ~(0x1 << (d->irq - MCF_IRQ_GPIO0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	writel(imr, MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void intc2_irq_gpio_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	imr = readl(MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	imr |= (0x1 << (d->irq - MCF_IRQ_GPIO0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	writel(imr, MCFSIM2_GPIOINTENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void intc2_irq_gpio_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct irq_chip intc2_irq_gpio_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	.name		= "CF-INTC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	.irq_mask	= intc2_irq_gpio_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	.irq_unmask	= intc2_irq_gpio_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.irq_ack	= intc2_irq_gpio_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int __init mcf_intc2_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* GPIO interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	for (irq = MCF_IRQ_GPIO0; (irq <= MCF_IRQ_GPIO7); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		irq_set_chip(irq, &intc2_irq_gpio_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		irq_set_handler(irq, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) arch_initcall(mcf_intc2_init);