^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * intc-2.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * General interrupt controller code for the many ColdFire cores that use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * interrupt controllers with 63 interrupt sources, organized as 56 fully-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * programmable + 7 fixed-level interrupt sources. This includes the 523x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * controllers, and the 547x and 548x families which have only one of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The external 7 fixed interrupts are part the the Edge Port unit of these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * ColdFire parts. They can be configured as level or edge triggered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * (C) Copyright 2009-2011, Greg Ungerer <gerg@snapgear.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Bit definitions for the ICR family of registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The EDGE Port interrupts are the fixed 7 external interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * They need some special treatment, for example they need to be acked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EINT0 64 /* Is not actually used, but spot reserved for it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EINT1 65 /* EDGE Port interrupt 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EINT7 71 /* EDGE Port interrupt 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #ifdef MCFICM_INTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define NR_VECS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define NR_VECS 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static void intc_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) unsigned int irq = d->irq - MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) unsigned long imraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 val, imrbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #ifdef MCFICM_INTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) imraddr = MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) imrbit = 0x1 << (irq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val = __raw_readl(imraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __raw_writel(val | imrbit, imraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static void intc_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int irq = d->irq - MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned long imraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 val, imrbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef MCFICM_INTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) imraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) imraddr = MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) imraddr += ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) imrbit = 0x1 << (irq & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Don't set the "maskall" bit! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if ((irq & 0x20) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) imrbit |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val = __raw_readl(imraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) __raw_writel(val & ~imrbit, imraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Only the external (or EDGE Port) interrupts need to be acknowledged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * here, as part of the IRQ handler. They only really need to be ack'ed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * if they are in edge triggered mode, but there is no harm in doing it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * for all types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void intc_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __raw_writeb(0x1 << (irq - EINT0), MCFEPORT_EPFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Each vector needs a unique priority and level associated with it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * We don't really care so much what they are, we don't rely on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * traditional priority interrupt scheme of the m68k/ColdFire. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * only needs to be set once for an interrupt, and we will never change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * these values once we have set them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static unsigned int intc_irq_startup(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int irq = d->irq - MCFINT_VECBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned long icraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef MCFICM_INTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) icraddr = (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) icraddr = MCFICM_INTC0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) icraddr += MCFINTC_ICR0 + (irq & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (__raw_readb(icraddr) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) __raw_writeb(intc_intpri--, icraddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if ((irq >= EINT1) && (irq <= EINT7)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) irq -= EINT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Set EPORT line as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) v = __raw_readb(MCFEPORT_EPDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) __raw_writeb(v & ~(0x1 << irq), MCFEPORT_EPDDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Set EPORT line as interrupt source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) v = __raw_readb(MCFEPORT_EPIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __raw_writeb(v | (0x1 << irq), MCFEPORT_EPIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) intc_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int intc_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int irq = d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 pa, tb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tb = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tb = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) tb = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Level triggered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (tb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) irq_set_handler(irq, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) irq -= EINT0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) pa = __raw_readw(MCFEPORT_EPPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pa = (pa & ~(0x3 << (irq * 2))) | (tb << (irq * 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) __raw_writew(pa, MCFEPORT_EPPAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static struct irq_chip intc_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "CF-INTC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .irq_startup = intc_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .irq_mask = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .irq_unmask = intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static struct irq_chip intc_irq_chip_edge_port = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "CF-INTC-EP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .irq_startup = intc_irq_startup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .irq_mask = intc_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .irq_unmask = intc_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .irq_ack = intc_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .irq_set_type = intc_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Mask all interrupt sources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) __raw_writel(0x1, MCFICM_INTC0 + MCFINTC_IMRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef MCFICM_INTC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) __raw_writel(0x1, MCFICM_INTC1 + MCFINTC_IMRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if ((irq >= EINT1) && (irq <=EINT7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) irq_set_chip(irq, &intc_irq_chip_edge_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) irq_set_chip(irq, &intc_irq_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) irq_set_handler(irq, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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