Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *	head.S -- common startup code for ColdFire CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	(C) Copyright 1999-2011, Greg Ungerer <gerg@snapgear.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mcfmmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *	If we don't have a fixed memory size, then lets build in code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *	to auto detect the DRAM size. Obviously this is the preferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *	method, and should work for most boards. It won't work for those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *	that do not have their RAM starting at address 0, and it only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *	works on SDRAM (not boards fitted with SRAM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #if CONFIG_RAMSIZE != 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) .macro GET_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	movel	#CONFIG_RAMSIZE,%d0	/* hard coded memory size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #elif defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)       defined(CONFIG_M5249) || defined(CONFIG_M525x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)       defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)       defined(CONFIG_M5307) || defined(CONFIG_M5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *	Not all these devices have exactly the same DRAM controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *	but the DCMR register is virtually identical - give or take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *	a couple of bits. The only exception is the 5272 devices, their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  *	DRAM controller is quite different.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) .macro GET_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	movel	MCFSIM_DMR0,%d0		/* get mask for 1st bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	btst	#0,%d0			/* check if region enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	andl	#0xfffc0000,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	beq	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	addl	#0x00040000,%d0		/* convert mask to size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	movel	MCFSIM_DMR1,%d1		/* get mask for 2nd bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	btst	#0,%d1			/* check if region enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	beq	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	andl	#0xfffc0000,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	beq	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	addl	#0x00040000,%d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	addl	%d1,%d0			/* total mem size in d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #elif defined(CONFIG_M5272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) .macro GET_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	movel	MCFSIM_CSOR7,%d0	/* get SDRAM address mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	andil	#0xfffff000,%d0		/* mask out chip select options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	negl	%d0			/* negate bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #elif defined(CONFIG_M520x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) .macro GET_MEM_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	clrl	%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	movel	MCFSIM_SDCS0, %d2	/* Get SDRAM chip select 0 config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	andl	#0x1f, %d2		/* Get only the chip select size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	beq	3f			/* Check if it is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	addql	#1, %d2			/* Form exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	moveql	#1, %d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	lsll	%d2, %d0		/* 2 ^ exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	movel	MCFSIM_SDCS1, %d2	/* Get SDRAM chip select 1 config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	andl	#0x1f, %d2		/* Get only the chip select size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	beq	4f			/* Check if it is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	addql	#1, %d2			/* Form exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	moveql	#1, %d1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	lsll	%d2, %d1		/* 2 ^ exponent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	addl	%d1, %d0		/* Total size of SDRAM in d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) .endm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #error "ERROR: I don't know how to probe your boards memory size?"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  *	Boards and platforms can do specific early hardware setup if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97)  *	they need to. Most don't need this, define away if not required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #ifndef PLATFORM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	PLATFORM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .global	_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .global _rambase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .global _ramvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .global	_ramstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .global	_ramend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #if defined(CONFIG_UBOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .global	_init_sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	During startup we store away the RAM setup. These are not in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *	bss, since their values are determined and written before the bss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  *	has been cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) _rambase:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) _ramvec:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) _ramstart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) _ramend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #if defined(CONFIG_UBOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) _init_sp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .long	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /*****************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) __HEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) _start0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	jmp	_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .global kernel_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .equ	kernel_pg_dir,_start0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .equ	.,_start0+0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  *	This is the codes first entry point. This is where it all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  *	begins...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) _start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	nop					/* filler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	movew	#0x2700, %sr			/* no interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	movel	#CACHE_INIT,%d0			/* disable cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	movec	%d0,%CACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #if defined(CONFIG_UBOOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	movel	%sp,_init_sp			/* save initial stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef CONFIG_MBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	movel	#CONFIG_MBAR+1,%d0		/* configured MBAR address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	movec	%d0,%MBAR			/* set it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	 *	Do any platform or board specific setup now. Most boards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	 *	don't need anything. Those exceptions are define this in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	 *	their board specific includes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	PLATFORM_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 *	Create basic memory configuration. Set VBR accordingly,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 *	and size memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	movel	#CONFIG_VECTORBASE,%a7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	movec   %a7,%VBR			/* set vectors addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	movel	%a7,_ramvec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	movel	#CONFIG_RAMBASE,%a7		/* mark the base of RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	movel	%a7,_rambase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	GET_MEM_SIZE				/* macro code determines size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	addl	%a7,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	movel	%d0,_ramend			/* set end ram addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 *	Now that we know what the memory is, lets enable cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 *	and get things moving. This is Coldfire CPU specific. Not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 *	all version cores have identical cache register setup. But
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 *	it is very similar. Define the exact settings in the headers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 *	then the code here is the same for all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	movel	#ACR0_MODE,%d0			/* set RAM region for caching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	movec	%d0,%ACR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	movel	#ACR1_MODE,%d0			/* anything else to cache? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	movec	%d0,%ACR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #ifdef ACR2_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	movel	#ACR2_MODE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	movec	%d0,%ACR2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	movel	#ACR3_MODE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	movec	%d0,%ACR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	movel	#CACHE_MODE,%d0			/* enable cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	movec	%d0,%CACR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 *	Identity mapping for the kernel region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	movel	#(MMUBASE+1),%d0		/* enable MMUBAR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	movec	%d0,%MMUBAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	movel	#MMUOR_CA,%d0			/* clear TLB entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	movel	%d0,MMUOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	movel	#0,%d0				/* set ASID to 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	movec	%d0,%asid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	movel	#MMUCR_EN,%d0			/* Enable the identity map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	movel	%d0,MMUCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	nop					/* sync i-pipeline */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	movel	#_vstart,%a0			/* jump to "virtual" space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	jmp	%a0@
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) _vstart:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #endif /* CONFIG_MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #ifdef CONFIG_ROMFS_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 *	Move ROM filesystem above bss :-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	lea	__bss_start,%a0			/* get start of bss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	lea	__bss_stop,%a1			/* set up destination  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	movel	%a0,%a2				/* copy of bss start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	movel	8(%a0),%d0			/* get size of ROMFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	addql	#8,%d0				/* allow for rounding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	andl	#0xfffffffc, %d0		/* whole words */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	addl	%d0,%a0				/* copy from end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	addl	%d0,%a1				/* copy from end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	movel	%a1,_ramstart			/* set start of ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) _copy_romfs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	movel	-(%a0),%d0			/* copy dword */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	movel	%d0,-(%a1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	cmpl	%a0,%a2				/* check if at end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	bne	_copy_romfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #else /* CONFIG_ROMFS_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	lea	__bss_stop,%a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	movel	%a1,_ramstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #endif /* CONFIG_ROMFS_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	 *	Zero out the bss region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	lea	__bss_start,%a0			/* get start of bss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	lea	__bss_stop,%a1			/* get end of bss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	clrl	%d0				/* set value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) _clear_bss:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	movel	%d0,(%a0)+			/* clear each word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	cmpl	%a0,%a1				/* check if at end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	bne	_clear_bss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	 *	Load the current task pointer and stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	lea	init_thread_union,%a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	lea	THREAD_SIZE(%a0),%sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #ifdef CONFIG_MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .global m68k_cputype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .global m68k_mmutype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .global m68k_fputype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .global m68k_machtype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	movel	#CPU_COLDFIRE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	movel	%d0,m68k_cputype		/* Mark us as a ColdFire */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	movel	#MMU_COLDFIRE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	movel	%d0,m68k_mmutype
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	movel	#FPUTYPE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	movel	%d0,m68k_fputype		/* Mark FPU type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	movel	#MACHINE,%d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	movel	%d0,m68k_machtype		/* Mark machine type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	lea	init_task,%a2			/* Set "current" init task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	 *	Assembler start up done, start code proper.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	jsr	start_kernel			/* start Linux kernel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	jmp	_exit				/* should never get here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*****************************************************************************/