Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * dma_timer.c -- Freescale ColdFire DMA Timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2007, Benedikt Spranger <b.spranger@linutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2008. Sebastian Siewior, Linutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mcfpit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DMA_TIMER_0	(0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DMA_TIMER_1	(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DMA_TIMER_2	(0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DMA_TIMER_3	(0xc0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DTMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DTXMR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DTER0	(MCF_IPSBAR + DMA_TIMER_0 + 0x403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DTRR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DTCR0	(MCF_IPSBAR + DMA_TIMER_0 + 0x408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DTCN0	(MCF_IPSBAR + DMA_TIMER_0 + 0x40c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DMA_FREQ    ((MCF_CLK / 2) / 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* DTMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DMA_DTMR_RESTART	(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DMA_DTMR_CLK_DIV_1	(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DMA_DTMR_CLK_DIV_16	(2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DMA_DTMR_ENABLE		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static u64 cf_dt_get_cycles(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	return __raw_readl(DTCN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static struct clocksource clocksource_cf_dt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	.name		= "coldfire_dma_timer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	.rating		= 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.read		= cf_dt_get_cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.mask		= CLOCKSOURCE_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static int __init  init_cf_dt_clocksource(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	 * We setup DMA timer 0 in free run mode. This incrementing counter is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	 * used as a highly precious clock source. With MCF_CLOCK = 150 MHz we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	 * get a ~213 ns resolution and the 32bit register will overflow almost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	 * every 15 minutes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	__raw_writeb(0x00, DTXMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	__raw_writeb(0x00, DTER0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	__raw_writel(0x00000000, DTRR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	__raw_writew(DMA_DTMR_CLK_DIV_16 | DMA_DTMR_ENABLE, DTMR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return clocksource_register_hz(&clocksource_cf_dt, DMA_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) arch_initcall(init_cf_dt_clocksource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CYC2NS_SCALE	((1000000 << CYC2NS_SCALE_FACTOR) / (DMA_FREQ / 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static unsigned long long cycles2ns(unsigned long cycl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	return (unsigned long long) ((unsigned long long)cycl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			CYC2NS_SCALE) >> CYC2NS_SCALE_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned long long sched_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	unsigned long cycl = __raw_readl(DTCN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	return cycles2ns(cycl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }