^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * device.c -- common ColdFire SoC device support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/fec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/traps.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/coldfire.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/mcfsim.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mcfuart.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/mcfqspi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/platform_data/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/dma-mcf-edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_data/mmc-esdhc-mcf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * All current ColdFire parts contain from 2, 3, 4 or 10 UARTS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct mcf_platform_uart mcf_uart_platform_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .mapbase = MCFUART_BASE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .irq = MCF_IRQ_UART0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .mapbase = MCFUART_BASE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .irq = MCF_IRQ_UART1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef MCFUART_BASE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mapbase = MCFUART_BASE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .irq = MCF_IRQ_UART2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifdef MCFUART_BASE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .mapbase = MCFUART_BASE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .irq = MCF_IRQ_UART3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #ifdef MCFUART_BASE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .mapbase = MCFUART_BASE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .irq = MCF_IRQ_UART4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #ifdef MCFUART_BASE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .mapbase = MCFUART_BASE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .irq = MCF_IRQ_UART5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #ifdef MCFUART_BASE6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .mapbase = MCFUART_BASE6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .irq = MCF_IRQ_UART6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #ifdef MCFUART_BASE7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .mapbase = MCFUART_BASE7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .irq = MCF_IRQ_UART7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #ifdef MCFUART_BASE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .mapbase = MCFUART_BASE8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .irq = MCF_IRQ_UART8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #ifdef MCFUART_BASE9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mapbase = MCFUART_BASE9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .irq = MCF_IRQ_UART9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static struct platform_device mcf_uart = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .name = "mcfuart",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .dev.platform_data = mcf_uart_platform_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #if IS_ENABLED(CONFIG_FEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_M5441x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define FEC_NAME "enet-fec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct fec_platform_data fec_pdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .phy = PHY_INTERFACE_MODE_RMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define FEC_PDATA (&fec_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FEC_NAME "fec"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FEC_PDATA NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Some ColdFire cores contain the Fast Ethernet Controller (FEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * block. It is Freescale's own hardware block. Some ColdFires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * have 2 of these.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct resource mcf_fec0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .start = MCFFEC_BASE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .start = MCF_IRQ_FECRX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .end = MCF_IRQ_FECRX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .start = MCF_IRQ_FECTX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .end = MCF_IRQ_FECTX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .start = MCF_IRQ_FECENTC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .end = MCF_IRQ_FECENTC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static struct platform_device mcf_fec0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .name = FEC_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .num_resources = ARRAY_SIZE(mcf_fec0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .resource = mcf_fec0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .dma_mask = &mcf_fec0.dev.coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .platform_data = FEC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef MCFFEC_BASE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static struct resource mcf_fec1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .start = MCFFEC_BASE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .start = MCF_IRQ_FECRX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .end = MCF_IRQ_FECRX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .start = MCF_IRQ_FECTX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .end = MCF_IRQ_FECTX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .start = MCF_IRQ_FECENTC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .end = MCF_IRQ_FECENTC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static struct platform_device mcf_fec1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = FEC_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .num_resources = ARRAY_SIZE(mcf_fec1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .resource = mcf_fec1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .dma_mask = &mcf_fec1.dev.coherent_dma_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .platform_data = FEC_PDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #endif /* MCFFEC_BASE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #endif /* CONFIG_FEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * The ColdFire QSPI module is an SPI protocol hardware block used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * on a number of different ColdFire CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static struct resource mcf_qspi_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .start = MCFQSPI_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .start = MCF_IRQ_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .end = MCF_IRQ_QSPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int mcf_cs_setup(struct mcfqspi_cs_control *cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) status = gpio_request(MCFQSPI_CS0, "MCFQSPI_CS0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pr_debug("gpio_request for MCFQSPI_CS0 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) goto fail0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) status = gpio_direction_output(MCFQSPI_CS0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pr_debug("gpio_direction_output for MCFQSPI_CS0 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) status = gpio_request(MCFQSPI_CS1, "MCFQSPI_CS1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) pr_debug("gpio_request for MCFQSPI_CS1 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) goto fail1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) status = gpio_direction_output(MCFQSPI_CS1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) pr_debug("gpio_direction_output for MCFQSPI_CS1 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) status = gpio_request(MCFQSPI_CS2, "MCFQSPI_CS2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pr_debug("gpio_request for MCFQSPI_CS2 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) goto fail2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) status = gpio_direction_output(MCFQSPI_CS2, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) pr_debug("gpio_direction_output for MCFQSPI_CS2 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #ifdef MCFQSPI_CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) status = gpio_request(MCFQSPI_CS3, "MCFQSPI_CS3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pr_debug("gpio_request for MCFQSPI_CS3 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) status = gpio_direction_output(MCFQSPI_CS3, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) pr_debug("gpio_direction_output for MCFQSPI_CS3 failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) gpio_free(MCFQSPI_CS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto fail3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) fail3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) gpio_free(MCFQSPI_CS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) fail2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) gpio_free(MCFQSPI_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) fail1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) gpio_free(MCFQSPI_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) fail0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void mcf_cs_teardown(struct mcfqspi_cs_control *cs_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef MCFQSPI_CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) gpio_free(MCFQSPI_CS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) gpio_free(MCFQSPI_CS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) gpio_free(MCFQSPI_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) gpio_free(MCFQSPI_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static void mcf_cs_select(struct mcfqspi_cs_control *cs_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u8 chip_select, bool cs_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (chip_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) gpio_set_value(MCFQSPI_CS0, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) gpio_set_value(MCFQSPI_CS1, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) gpio_set_value(MCFQSPI_CS2, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #ifdef MCFQSPI_CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) gpio_set_value(MCFQSPI_CS3, cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void mcf_cs_deselect(struct mcfqspi_cs_control *cs_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 chip_select, bool cs_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) switch (chip_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) gpio_set_value(MCFQSPI_CS0, !cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) gpio_set_value(MCFQSPI_CS1, !cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) gpio_set_value(MCFQSPI_CS2, !cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #ifdef MCFQSPI_CS3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) gpio_set_value(MCFQSPI_CS3, !cs_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static struct mcfqspi_cs_control mcf_cs_control = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .setup = mcf_cs_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .teardown = mcf_cs_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .select = mcf_cs_select,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .deselect = mcf_cs_deselect,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct mcfqspi_platform_data mcf_qspi_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .bus_num = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .num_chipselect = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .cs_control = &mcf_cs_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static struct platform_device mcf_qspi = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .name = "mcfqspi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .num_resources = ARRAY_SIZE(mcf_qspi_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .resource = mcf_qspi_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .dev.platform_data = &mcf_qspi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static struct resource mcf_i2c0_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .start = MCFI2C_BASE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .start = MCF_IRQ_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .end = MCF_IRQ_I2C0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static struct platform_device mcf_i2c0 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .num_resources = ARRAY_SIZE(mcf_i2c0_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .resource = mcf_i2c0_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #ifdef MCFI2C_BASE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static struct resource mcf_i2c1_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .start = MCFI2C_BASE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .start = MCF_IRQ_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .end = MCF_IRQ_I2C1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static struct platform_device mcf_i2c1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .id = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .num_resources = ARRAY_SIZE(mcf_i2c1_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .resource = mcf_i2c1_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif /* MCFI2C_BASE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #ifdef MCFI2C_BASE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct resource mcf_i2c2_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .start = MCFI2C_BASE2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .start = MCF_IRQ_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .end = MCF_IRQ_I2C2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct platform_device mcf_i2c2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .id = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .num_resources = ARRAY_SIZE(mcf_i2c2_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .resource = mcf_i2c2_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif /* MCFI2C_BASE2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #ifdef MCFI2C_BASE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct resource mcf_i2c3_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .start = MCFI2C_BASE3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .start = MCF_IRQ_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .end = MCF_IRQ_I2C3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static struct platform_device mcf_i2c3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .id = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .num_resources = ARRAY_SIZE(mcf_i2c3_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .resource = mcf_i2c3_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #endif /* MCFI2C_BASE3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifdef MCFI2C_BASE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static struct resource mcf_i2c4_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .start = MCFI2C_BASE4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .start = MCF_IRQ_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .end = MCF_IRQ_I2C4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct platform_device mcf_i2c4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .id = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .num_resources = ARRAY_SIZE(mcf_i2c4_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .resource = mcf_i2c4_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif /* MCFI2C_BASE4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #ifdef MCFI2C_BASE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct resource mcf_i2c5_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .start = MCFI2C_BASE5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .start = MCF_IRQ_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .end = MCF_IRQ_I2C5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static struct platform_device mcf_i2c5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "imx1-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .id = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .num_resources = ARRAY_SIZE(mcf_i2c5_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .resource = mcf_i2c5_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #endif /* MCFI2C_BASE5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #endif /* IS_ENABLED(CONFIG_I2C_IMX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #ifdef MCFEDMA_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct dma_slave_map mcf_edma_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { "dreq0", "rx-tx", MCF_EDMA_FILTER_PARAM(0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { "dreq1", "rx-tx", MCF_EDMA_FILTER_PARAM(1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { "uart.0", "rx", MCF_EDMA_FILTER_PARAM(2) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { "uart.0", "tx", MCF_EDMA_FILTER_PARAM(3) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { "uart.1", "rx", MCF_EDMA_FILTER_PARAM(4) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { "uart.1", "tx", MCF_EDMA_FILTER_PARAM(5) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { "uart.2", "rx", MCF_EDMA_FILTER_PARAM(6) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { "uart.2", "tx", MCF_EDMA_FILTER_PARAM(7) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { "timer0", "rx-tx", MCF_EDMA_FILTER_PARAM(8) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { "timer1", "rx-tx", MCF_EDMA_FILTER_PARAM(9) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { "timer2", "rx-tx", MCF_EDMA_FILTER_PARAM(10) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { "timer3", "rx-tx", MCF_EDMA_FILTER_PARAM(11) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { "fsl-dspi.0", "rx", MCF_EDMA_FILTER_PARAM(12) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { "fsl-dspi.0", "tx", MCF_EDMA_FILTER_PARAM(13) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { "fsl-dspi.1", "rx", MCF_EDMA_FILTER_PARAM(14) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { "fsl-dspi.1", "tx", MCF_EDMA_FILTER_PARAM(15) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct mcf_edma_platform_data mcf_edma_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .dma_channels = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .slave_map = mcf_edma_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .slavecnt = ARRAY_SIZE(mcf_edma_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static struct resource mcf_edma_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .start = MCFEDMA_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .end = MCFEDMA_BASE + MCFEDMA_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .start = MCFEDMA_IRQ_INTR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .end = MCFEDMA_IRQ_INTR0 + 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .name = "edma-tx-00-15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .start = MCFEDMA_IRQ_INTR16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .end = MCFEDMA_IRQ_INTR16 + 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .name = "edma-tx-16-55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .start = MCFEDMA_IRQ_INTR56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .end = MCFEDMA_IRQ_INTR56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .name = "edma-tx-56-63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .start = MCFEDMA_IRQ_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .end = MCFEDMA_IRQ_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .name = "edma-err",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static u64 mcf_edma_dmamask = DMA_BIT_MASK(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct platform_device mcf_edma = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "mcf-edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .num_resources = ARRAY_SIZE(mcf_edma_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .resource = mcf_edma_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .dev = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .dma_mask = &mcf_edma_dmamask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .coherent_dma_mask = DMA_BIT_MASK(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .platform_data = &mcf_edma_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #endif /* MCFEDMA_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef MCFSDHC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static struct mcf_esdhc_platform_data mcf_esdhc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .max_bus_width = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .cd_type = ESDHC_CD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct resource mcf_esdhc_resources[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .start = MCFSDHC_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .end = MCFSDHC_BASE + MCFSDHC_SIZE - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .flags = IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .start = MCF_IRQ_SDHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .end = MCF_IRQ_SDHC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .flags = IORESOURCE_IRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static struct platform_device mcf_esdhc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "sdhci-esdhc-mcf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .id = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .num_resources = ARRAY_SIZE(mcf_esdhc_resources),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .resource = mcf_esdhc_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .dev.platform_data = &mcf_esdhc_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #endif /* MCFSDHC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static struct platform_device *mcf_devices[] __initdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) &mcf_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #if IS_ENABLED(CONFIG_FEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) &mcf_fec0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #ifdef MCFFEC_BASE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) &mcf_fec1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) &mcf_qspi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #if IS_ENABLED(CONFIG_I2C_IMX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) &mcf_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef MCFI2C_BASE1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) &mcf_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #ifdef MCFI2C_BASE2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) &mcf_i2c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #ifdef MCFI2C_BASE3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &mcf_i2c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef MCFI2C_BASE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) &mcf_i2c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #ifdef MCFI2C_BASE5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) &mcf_i2c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #ifdef MCFEDMA_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &mcf_edma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #ifdef MCFSDHC_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) &mcf_esdhc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * Some ColdFire UARTs let you set the IRQ line to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static void __init mcf_uart_set_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #ifdef MCFUART_UIVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* UART0 interrupt setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI1, MCFSIM_UART1ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) writeb(MCF_IRQ_UART0, MCFUART_BASE0 + MCFUART_UIVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mcf_mapirq2imr(MCF_IRQ_UART0, MCFINTC_UART0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* UART1 interrupt setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) writeb(MCFSIM_ICR_LEVEL6 | MCFSIM_ICR_PRI2, MCFSIM_UART2ICR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) writeb(MCF_IRQ_UART1, MCFUART_BASE1 + MCFUART_UIVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mcf_mapirq2imr(MCF_IRQ_UART1, MCFINTC_UART1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static int __init mcf_init_devices(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mcf_uart_set_irq();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) platform_add_devices(mcf_devices, ARRAY_SIZE(mcf_devices));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) arch_initcall(mcf_init_devices);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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