^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * m68VZ328.c - 68VZ328 specific config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1993 Hamish Macdonald
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1999 D. Jeff Dionne
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2001 Georges Menie, Ken Desmet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * License. See the file COPYING in the main directory of this archive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rtc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/MC68VZ328.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/bootstd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifdef CONFIG_INIT_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "bootlogo-vz.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int m68328_hwclk(int set, struct rtc_time *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Init Drangon Engine hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #if defined(CONFIG_DRAGEN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static void m68vz328_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifdef CONFIG_INIT_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PBDATA |= 0x20; /* disable CCFL light */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PKDATA |= 0x4; /* disable LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) LCKCON = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "reset\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "moveal #0x04000000, %a0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "moveal 0(%a0), %sp\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "moveal 4(%a0), %a0\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "jmp (%a0)"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static void __init init_hardware(char *command, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #ifdef CONFIG_DIRECT_IO_ACCESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) SCR = 0x10; /* allow user access to internal registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* CSGB Init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CSGBB = 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CSB = 0x1a1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* CS8900 init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* PK3: hardware sleep function pin, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PKSEL |= PK(3); /* select pin as I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PKDIR |= PK(3); /* select pin as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PKDATA |= PK(3); /* set pin high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* PF5: hardware reset function pin, active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PFSEL |= PF(5); /* select pin as I/O */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PFDIR |= PF(5); /* select pin as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PFDATA &= ~PF(5); /* set pin low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* cs8900 hardware reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PFDATA |= PF(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { int i; for (i = 0; i < 32000; ++i); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PFDATA &= ~PF(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* INT1 enable (cs8900 IRQ) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PDPOL &= ~PD(1); /* active high signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PDIQEG &= ~PD(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PDIRQEN |= PD(1); /* IRQ enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef CONFIG_INIT_LCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* initialize LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) LSSA = (long) screen_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LVPW = 0x14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LXMAX = 0x140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) LYMAX = 0xef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) LRRA = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) LPXCD = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) LPICF = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) LPOLCF = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) LCKCON = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PCPDEN = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PCSEL = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Enable LCD controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PKDIR |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PKSEL |= 0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PKDATA &= ~0x4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Enable CCFL backlighting circuit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PBDIR |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PBSEL |= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PBDATA &= ~0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* contrast control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PFDIR |= 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PFSEL &= ~0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PWMR = 0x037F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Init RT-Control uCdimm hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #elif defined(CONFIG_UCDIMM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void m68vz328_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) local_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) asm volatile (
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "moveal #0x10c00000, %a0;\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "moveb #0, 0xFFFFF300;\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "moveal 0(%a0), %sp;\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "moveal 4(%a0), %a0;\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) "jmp (%a0);\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned char *cs8900a_hwaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int errno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) _bsc0(char *, getserialnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) _bsc1(unsigned char *, gethwaddr, int, a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) _bsc1(char *, getbenv, char *, a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void __init init_hardware(char *command, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) pr_info("uCdimm serial string [%s]\n", getserialnum());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) p = cs8900a_hwaddr = gethwaddr(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) pr_info("uCdimm hwaddr %pM\n", p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) p = getbenv("APPEND");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) strcpy(p, command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) command[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void m68vz328_reset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void __init init_hardware(char *command, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /***************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void __init config_BSP(char *command, int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pr_info("68VZ328 DragonBallVZ support (c) 2001 Lineo, Inc.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) init_hardware(command, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) mach_sched_init = hw_timer_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mach_hwclk = m68328_hwclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) mach_reset = m68vz328_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /***************************************************************************/
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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