^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pci.c - Low-Level PCI Access in IA-64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Derived from bios32.c of i386 tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Bjorn Helgaas <bjorn.helgaas@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2004 Silicon Graphics, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Note: Above list of copyright holders is incomplete...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pci-acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/sal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Low-level SAL-based PCI configuration access functions. Note that SAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * calls are already serialized (via sal_lock), so we don't need another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * synchronization mechanism here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* SAL 3.2 adds support for extended config space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int reg, int len, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 addr, data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int mode, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if ((seg | reg) <= 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) result = ia64_sal_pci_config_read(addr, mode, len, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *value = (u32) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int reg, int len, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int mode, result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if ((seg | reg) <= 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) result = ia64_sal_pci_config_write(addr, mode, len, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (result != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int size, u32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return raw_pci_read(pci_domain_nr(bus), bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) int size, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return raw_pci_write(pci_domain_nr(bus), bus->number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) devfn, where, size, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pci_ops pci_root_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .read = pci_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .write = pci_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct pci_root_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct acpi_pci_root_info common;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pci_controller controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct list_head io_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static unsigned int new_space(u64 phys_base, int sparse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u64 mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (phys_base == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0; /* legacy I/O port space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mmio_base = (u64) ioremap(phys_base, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) for (i = 0; i < num_io_spaces; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) if (io_space[i].mmio_base == mmio_base &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) io_space[i].sparse == sparse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (num_io_spaces == MAX_IO_SPACES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_err("PCI: Too many IO port spaces "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) i = num_io_spaces++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) io_space[i].mmio_base = mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) io_space[i].sparse = sparse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int add_io_space(struct device *dev, struct pci_root_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct resource_entry *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct resource_entry *iospace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct resource *resource, *res = entry->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long base, min, max, base_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int sparse = 0, space_nr, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) len = strlen(info->common.name) + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) iospace = resource_list_create_entry(NULL, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (!iospace) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dev, "PCI: No memory for %s I/O port space\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) info->common.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (res->flags & IORESOURCE_IO_SPARSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sparse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) space_nr = new_space(entry->offset, sparse);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (space_nr == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) goto free_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) name = (char *)(iospace + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) min = res->start - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) max = res->end - entry->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) base = __pa(io_space[space_nr].mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) base_port = IO_SPACE_BASE(space_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->common.name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) base_port + min, base_port + max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * The SDM guarantees the legacy 0-64K space is sparse, but if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * mapping is done by the processor (not the bridge), ACPI may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * mark it as sparse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (space_nr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) sparse = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) resource = iospace->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) resource->name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) resource->flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (insert_resource(&iomem_resource, resource)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "can't allocate host bridge io space resource %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) resource);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) goto free_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) entry->offset = base_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) res->start = min + base_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) res->end = max + base_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) resource_list_add_tail(iospace, &info->io_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) free_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) resource_list_free_entry(iospace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * An IO port or MMIO resource assigned to a PCI host bridge may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * consumed by the host bridge itself or available to its child
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * bus/devices. The ACPI specification defines a bit (Producer/Consumer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * to tell whether the resource is consumed by the host bridge itself,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * but firmware hasn't used that bit consistently, so we can't rely on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * On x86 and IA64 platforms, all IO port and MMIO resources are assumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * to be available to child bus/devices except one special case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * IO port [0xCF8-0xCFF] is consumed by the host bridge itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * to access PCI configuration space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * So explicitly filter out PCI CFG IO ports[0xCF8-0xCFF].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static bool resource_is_pcicfg_ioport(struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return (res->flags & IORESOURCE_IO) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) res->start == 0xCF8 && res->end == 0xCFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct device *dev = &ci->bridge->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct pci_root_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct resource_entry *entry, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) status = acpi_pci_probe_root_resources(ci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (status > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) info = container_of(ci, struct pci_root_info, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) res = entry->res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (res->flags & IORESOURCE_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * HP's firmware has a hack to work around a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * Windows bug. Ignore these tiny memory ranges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (resource_size(res) <= 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) resource_list_del(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) insert_resource(&iomem_resource,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) resource_list_add_tail(entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) &info->io_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) } else if (res->flags & IORESOURCE_IO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (resource_is_pcicfg_ioport(entry->res))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) resource_list_destroy_entry(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) else if (add_io_space(dev, info, entry))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) resource_list_destroy_entry(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void pci_acpi_root_release_info(struct acpi_pci_root_info *ci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct pci_root_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct resource_entry *entry, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) info = container_of(ci, struct pci_root_info, common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) resource_list_for_each_entry_safe(entry, tmp, &info->io_resources) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) release_resource(entry->res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) resource_list_destroy_entry(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) kfree(info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static struct acpi_pci_root_ops pci_acpi_root_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .pci_ops = &pci_root_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .release_info = pci_acpi_root_release_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .prepare_resources = pci_acpi_root_prepare_resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct acpi_device *device = root->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct pci_root_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) info = kzalloc(sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (!info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) dev_err(&device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "pci_bus %04x:%02x: ignored (out of memory)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) root->segment, (int)root->secondary.start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) info->controller.segment = root->segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) info->controller.companion = device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) info->controller.node = acpi_get_node(device->handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) INIT_LIST_HEAD(&info->io_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return acpi_pci_root_create(root, &pci_acpi_root_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) &info->common, &info->controller);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * We pass NULL as parent to pci_create_root_bus(), so if it is not NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * here, pci_create_root_bus() has been called by someone else and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * sysdata is likely to be different from what we expect. Let it go in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (!bridge->dev.parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct pci_controller *controller = bridge->bus->sysdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ACPI_COMPANION_SET(&bridge->dev, controller->companion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) void pcibios_fixup_device_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!dev->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) for (idx = 0; idx < PCI_BRIDGE_RESOURCES; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct resource *r = &dev->resource[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!r->flags || r->parent || !r->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) pci_claim_resource(dev, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!dev->bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct resource *r = &dev->resource[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!r->flags || r->parent || !r->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) pci_claim_bridge_resource(dev, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Called after each bus is probed, but before its children are examined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void pcibios_fixup_bus(struct pci_bus *b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (b->self) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pci_read_bridge_bases(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pcibios_fixup_bridge_resources(b->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) list_for_each_entry(dev, &b->devices, bus_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pcibios_fixup_device_resources(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) void pcibios_add_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) acpi_pci_add_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) void pcibios_remove_bus(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) acpi_pci_remove_bus(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) void pcibios_set_master (struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* No special bus mastering setup handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) pcibios_enable_device (struct pci_dev *dev, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ret = pci_enable_resources(dev, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (!pci_dev_msi_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return acpi_pci_irq_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pcibios_disable_device (struct pci_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) BUG_ON(atomic_read(&dev->enable_cnt));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!pci_dev_msi_enabled(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) acpi_pci_irq_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * pci_get_legacy_mem - generic legacy mem routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * @bus: bus to get legacy memory base address for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Find the base of legacy memory for @bus. This is typically the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * megabyte of bus address space for @bus or is simply 0 on platforms whose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * chipsets support legacy I/O and memory routing. Returns the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * or an error pointer if an error occurred.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * This is the ia64 generic version of this routine. Other platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * are free to override it with a machine vector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) char *pci_get_legacy_mem(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return (char *)__IA64_UNCACHED_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * pci_mmap_legacy_page_range - map legacy memory space to userland
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @bus: bus whose legacy space we're mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @vma: vma passed in by mmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Map legacy memory space for this device back to userspace using a machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * vector to get the base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) enum pci_mmap_state mmap_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned long size = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) pgprot_t prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) char *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* We only support mmap'ing of legacy memory space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (mmap_state != pci_mmap_mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -ENOSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * Avoid attribute aliasing. See Documentation/ia64/aliasing.rst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) vma->vm_page_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) addr = pci_get_legacy_mem(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (IS_ERR(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return PTR_ERR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) vma->vm_page_prot = prot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) size, vma->vm_page_prot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * pci_legacy_read - read from legacy I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @bus: bus to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @port: legacy port value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @val: caller allocated storage for returned value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @size: number of bytes to read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * Simply reads @size bytes from @port and puts the result in @val.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * Again, this (and the write routine) are generic versions that can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * overridden by the platform. This is necessary on platforms that don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * support legacy I/O routing or that hard fail on legacy I/O timeouts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int ret = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *val = inb(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *val = inw(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *val = inl(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * pci_legacy_write - perform a legacy I/O write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) * @bus: bus pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * @port: port to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * @val: value to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * @size: number of bytes to write from @val
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * Simply writes @size bytes of @val to @port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int ret = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) switch (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) outb(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) outw(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) outl(val, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * set_pci_cacheline_size - determine cacheline size for PCI devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * We want to use the line-size of the outer-most cache. We assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * that this line-size is the same for all CPUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static void __init set_pci_dfl_cacheline_size(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) unsigned long levels, unique_caches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) pal_cache_config_info_t cci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) status = ia64_pal_cache_summary(&levels, &unique_caches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) pr_err("%s: ia64_pal_cache_summary() failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "(status=%ld)\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) status = ia64_pal_cache_config_info(levels - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* cache_type (data_or_unified)= */ 2, &cci);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) pr_err("%s: ia64_pal_cache_config_info() failed "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "(status=%ld)\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int __init pcibios_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) set_pci_dfl_cacheline_size();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) subsys_initcall(pcibios_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags