Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Derived from fixup.c of i386 tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/vgaarb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/screen_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/uv/uv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Fixup to mark boot BIOS video selected by BIOS before it changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * From information provided by "Jon Smirl" <jonsmirl@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  * The standard boot ROM sequence for an x86 machine uses the BIOS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  * to select an initial video card for boot display. This boot video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * card will have its BIOS copied to 0xC0000 in system RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  * IORESOURCE_ROM_SHADOW is used to associate the boot video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)  * card with this copy. On laptops this copy has to be used since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)  * the main ROM may be compressed or combined with another image.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * See pci_map_rom() for use of this flag. Before marking the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * with IORESOURCE_ROM_SHADOW check if a vga_default_device is already set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * by either arch code or vga-arbitration; if so only apply the fixup to this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  * already-determined primary video card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void pci_fixup_video(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct pci_dev *bridge;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct pci_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u16 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	if (is_uv_system())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	/* Maybe, this machine supports legacy memory map. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* Is VGA routed to us? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	bus = pdev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	while (bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		bridge = bus->self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		 * From information provided by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		 * "David Miller" <davem@davemloft.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		 * The bridge control register is valid for PCI header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		 * type BRIDGE, or CARDBUS. Host to PCI controllers use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		 * PCI header type NORMAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		if (bridge && (pci_is_bridge(bridge))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 						&config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			if (!(config & PCI_BRIDGE_CTL_VGA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		bus = bus->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	if (!vga_default_device() || pdev == vga_default_device()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		pci_read_config_word(pdev, PCI_COMMAND, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		if (config & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			res = &pdev->resource[PCI_ROM_RESOURCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			pci_disable_rom(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			if (res->parent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 				release_resource(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 			res->start = 0xC0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			res->end = res->start + 0x20000 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			res->flags = IORESOURCE_MEM | IORESOURCE_ROM_SHADOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 				     IORESOURCE_PCI_FIXED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			dev_info(&pdev->dev, "Video device with shadowed ROM at %pR\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 				 res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 				PCI_CLASS_DISPLAY_VGA, 8, pci_fixup_video);