^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2000 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 32-bit integer division.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This code is based on the application note entitled "Divide, Square Root
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and Remainder Algorithms for the IA-64 Architecture". This document
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * is available as Intel document number 248725-002 or via the web at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * http://developer.intel.com/software/opensource/numerics/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * For more details on the theory behind these algorithms, see "IA-64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * and Elementary Functions" by Peter Markstein; HP Professional Books
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef MODULO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define OP mod
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define OP div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #ifdef UNSIGNED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define SGN u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) # define EXTEND zxt4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # define INT_TO_FP(a,b) fcvt.xuf.s1 a=b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) # define FP_TO_INT(a,b) fcvt.fxu.trunc.s1 a=b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) # define SGN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) # define EXTEND sxt4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) # define INT_TO_FP(a,b) fcvt.xf a=b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) # define FP_TO_INT(a,b) fcvt.fx.trunc.s1 a=b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PASTE1(a,b) a##b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PASTE(a,b) PASTE1(a,b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define NAME PASTE(PASTE(__,SGN),PASTE(OP,si3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GLOBAL_ENTRY(NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .regstk 2,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) // Transfer inputs to FP registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) mov r2 = 0xffdd // r2 = -34 + 65535 (fp reg format bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) EXTEND in0 = in0 // in0 = a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) EXTEND in1 = in1 // in1 = b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) setf.sig f8 = in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) setf.sig f9 = in1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef MODULO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) sub in1 = r0, in1 // in1 = -b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) // Convert the inputs to FP, to avoid FP software-assist faults.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) INT_TO_FP(f8, f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) INT_TO_FP(f9, f9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) setf.exp f7 = r2 // f7 = 2^-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) frcpa.s1 f6, p6 = f8, f9 // y0 = frcpa(b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (p6) fmpy.s1 f8 = f8, f6 // q0 = a*y0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) (p6) fnma.s1 f6 = f9, f6, f1 // e0 = -b*y0 + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef MODULO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) setf.sig f9 = in1 // f9 = -b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) (p6) fma.s1 f8 = f6, f8, f8 // q1 = e0*q0 + q0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (p6) fma.s1 f6 = f6, f6, f7 // e1 = e0*e0 + 2^-34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #ifdef MODULO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) setf.sig f7 = in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (p6) fma.s1 f6 = f6, f8, f8 // q2 = e1*q1 + q1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FP_TO_INT(f6, f6) // q = trunc(q2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #ifdef MODULO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) xma.l f6 = f6, f9, f7 // r = q*(-b) + a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) getf.sig r8 = f6 // transfer result to result register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) END(NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) EXPORT_SYMBOL(NAME)