^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define EMITS_PT_NOTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define RO_EXCEPTION_TABLE_ALIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm-generic/vmlinux.lds.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) OUTPUT_FORMAT("elf64-ia64-little")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) OUTPUT_ARCH(ia64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ENTRY(phys_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) jiffies = jiffies_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PHDRS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) text PT_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) percpu PT_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) data PT_LOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) note PT_NOTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) unwind 0x70000001; /* PT_IA_64_UNWIND, but ld doesn't match the name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) SECTIONS {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * unwind exit sections must be discarded before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * the rest of the sections get included.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /DISCARD/ : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *(.IA_64.unwind.exit.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *(.IA_64.unwind_info.exit.text)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *(.comment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *(.note)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) v = PAGE_OFFSET; /* this symbol is here to make debugging easier... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) phys_start = _start - LOAD_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) code : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) } :text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) . = KERNEL_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) _text = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) _stext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .text : AT(ADDR(.text) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __start_ivt_text = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *(.text..ivt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __end_ivt_text = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) TEXT_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) SCHED_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) CPUIDLE_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) LOCK_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) KPROBES_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) IRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) SOFTIRQENTRY_TEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *(.gnu.linkonce.t*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .text2 : AT(ADDR(.text2) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *(.text2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .text..lock : AT(ADDR(.text..lock) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *(.text..lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) _etext = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Read-only data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MCA table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) . = ALIGN(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __mca_table : AT(ADDR(__mca_table) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __start___mca_table = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *(__mca_table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __stop___mca_table = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .data..patch.phys_stack_reg : AT(ADDR(.data..patch.phys_stack_reg) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) __start___phys_stack_reg_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) *(.data..patch.phys_stack_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) __end___phys_stack_reg_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Global data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) _data = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Unwind info & table: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) . = ALIGN(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .IA_64.unwind_info : AT(ADDR(.IA_64.unwind_info) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *(.IA_64.unwind_info*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .IA_64.unwind : AT(ADDR(.IA_64.unwind) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __start_unwind = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) *(.IA_64.unwind*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) __end_unwind = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } :text :unwind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) code_continues2 : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } :text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) RO_DATA(4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .opd : AT(ADDR(.opd) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __start_opd = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *(.opd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __end_opd = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Initialization code and data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __init_begin = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) INIT_TEXT_SECTION(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) INIT_DATA_SECTION(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .data..patch.vtop : AT(ADDR(.data..patch.vtop) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) __start___vtop_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) *(.data..patch.vtop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __end___vtop_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .data..patch.rse : AT(ADDR(.data..patch.rse) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) __start___rse_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) *(.data..patch.rse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) __end___rse_patchlist = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .data..patch.mckinley_e9 : AT(ADDR(.data..patch.mckinley_e9) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) __start___mckinley_e9_bundles = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *(.data..patch.mckinley_e9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) __end___mckinley_e9_bundles = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) . = ALIGN(PERCPU_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) __cpu0_per_cpu = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) . = . + PERCPU_PAGE_SIZE; /* cpu0 per-cpu space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) __init_end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .data..page_aligned : AT(ADDR(.data..page_aligned) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PAGE_ALIGNED_DATA(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) __start_gate_section = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) *(.data..gate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) __stop_gate_section = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * make sure the gate page doesn't expose
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * kernel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) . = ALIGN(PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Per-cpu data: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) . = ALIGN(PERCPU_PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PERCPU_VADDR(SMP_CACHE_BYTES, PERCPU_ADDR, :percpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __phys_per_cpu_start = __per_cpu_load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * ensure percpu data fits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * into percpu page size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) . = __phys_per_cpu_start + PERCPU_PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) data : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) } :data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .data : AT(ADDR(.data) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) _sdata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) INIT_TASK_DATA(PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) CACHELINE_ALIGNED_DATA(SMP_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) READ_MOSTLY_DATA(SMP_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DATA_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) *(.data1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) *(.gnu.linkonce.d*)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) CONSTRUCTORS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BUG_TABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) . = ALIGN(16); /* gp must be 16-byte aligned for exc. table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .got : AT(ADDR(.got) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *(.got.plt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *(.got)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) __gp = ADDR(.got) + 0x200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * We want the small data sections together,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * so single-instruction offsets can access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * them all, and initialized data all before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * uninitialized, so we can shorten the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * on-disk segment size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .sdata : AT(ADDR(.sdata) - LOAD_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *(.sdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *(.sdata1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *(.srdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) _edata = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) BSS_SECTION(0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) _end = .;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) code : {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) } :text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) STABS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DWARF_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ELF_DETAILS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Default discards */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DISCARDS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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