^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/ia64/kernel/relocate_kernel.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Relocate kexec'able kernel and start it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2005 Hewlett-Packard Development Company, L.P.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2005 Khalid Aziz <khalid.aziz@hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2005 Intel Corp, Zou Nan hai <nanhai.zou@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/kregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/mca_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Must be relocatable PIC code callable as a C function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) GLOBAL_ENTRY(relocate_new_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) alloc r31=ar.pfs,4,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .reloc_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) rsm psr.i| psr.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) mov r2=ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) flushrs // must be first insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) dep r2=0,r2,61,3 //to physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) //first switch to physical mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) add r3=1f-.reloc_entry, r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) movl r16 = IA64_PSR_AC|IA64_PSR_BN|IA64_PSR_IC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) mov ar.rsc=0 // put RSE in enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) add sp=(memory_stack_end - 16 - .reloc_entry),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) add r8=(register_stack - .reloc_entry),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mov r18=ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mov ar.bspstore=r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mov cr.ipsr=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mov cr.iip=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mov cr.ifs=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mov ar.rnat=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) rfi // note: this unmask MCA/INIT (psr.mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) //physical mode code begin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mov b6=in1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dep r28=0,in2,61,3 //to physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) // purge all TC entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define O(member) IA64_CPUINFO_##member##_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) GET_THIS_PADDR(r2, ia64_cpu_info) // load phys addr of cpu_info into r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) addl r17=O(PTCE_STRIDE),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) addl r2=O(PTCE_BASE),r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) ld8 r18=[r2],(O(PTCE_COUNT)-O(PTCE_BASE));; // r18=ptce_base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ld4 r19=[r2],4 // r19=ptce_count[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ld4 r21=[r17],4 // r21=ptce_stride[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ld4 r20=[r2] // r20=ptce_count[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) ld4 r22=[r17] // r22=ptce_stride[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mov r24=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) adds r20=-1,r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #undef O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) cmp.ltu p6,p7=r24,r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (p7) br.cond.dpnt.few 4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mov ar.lc=r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ptc.e r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) add r18=r22,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) br.cloop.sptk.few 3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) add r18=r21,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) add r24=1,r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) br.sptk.few 2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) // purge TR entry for kernel text and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) movl r16=KERNEL_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mov r18=KERNEL_TR_PAGE_SHIFT<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ptr.i r16, r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ptr.d r16, r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) // purge TR entry for pal code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mov r16=in3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) mov r18=IA64_GRANULE_SHIFT<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ptr.i r16,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) // purge TR entry for stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mov r16=IA64_KR(CURRENT_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) shl r16=r16,IA64_GRANULE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) movl r19=PAGE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) add r16=r19,r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mov r18=IA64_GRANULE_SHIFT<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ptr.d r16,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) //copy segments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) movl r16=PAGE_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) mov r30=in0 // in0 is page_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) br.sptk.few .dest_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ld8 r30=[in0], 8;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .dest_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tbit.z p0, p6=r30, 0;; // 0x1 dest page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (p6) and r17=r30, r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (p6) br.cond.sptk.few .loop;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) tbit.z p0, p6=r30, 1;; // 0x2 indirect page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) (p6) and in0=r30, r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (p6) br.cond.sptk.few .loop;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) tbit.z p0, p6=r30, 2;; // 0x4 end flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) (p6) br.cond.sptk.few .end_loop;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) tbit.z p6, p0=r30, 3;; // 0x8 source page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) (p6) br.cond.sptk.few .loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) and r18=r30, r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) // simple copy page, may optimize later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) movl r14=PAGE_SIZE/8 - 1;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) mov ar.lc=r14;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ld8 r14=[r18], 8;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) st8 [r17]=r14;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) fc.i r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) add r17=8, r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) br.ctop.sptk.few 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) br.sptk.few .loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .end_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) sync.i // for fc.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) srlz.d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) br.call.sptk.many b0=b6;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .align 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) memory_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .fill 8192, 1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) memory_stack_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) register_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .fill 8192, 1, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) register_stack_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) relocate_new_kernel_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) END(relocate_new_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .global relocate_new_kernel_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) relocate_new_kernel_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) data8 relocate_new_kernel_end - relocate_new_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GLOBAL_ENTRY(ia64_dump_cpu_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) alloc loc0=ar.pfs,1,2,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mov ar.rsc=0 // put RSE in enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) add loc1=4*8, in0 // save r4 and r5 first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) flushrs // flush dirty regs to backing store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) st8 [loc1]=r4, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) st8 [loc1]=r5, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) add loc1=32*8, in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mov r4=ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) st8 [in0]=r0, 8 // r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) st8 [loc1]=r4, 8 // rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mov r5=pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) st8 [in0]=r1, 8 // r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) st8 [loc1]=r5, 8 // pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) mov r4=b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) st8 [in0]=r2, 8 // r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) st8 [loc1]=r4, 8 // b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) mov r5=b1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) st8 [in0]=r3, 24 // r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) st8 [loc1]=r5, 8 // b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) mov r4=b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) st8 [in0]=r6, 8 // r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) st8 [loc1]=r4, 8 // b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) mov r5=b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) st8 [in0]=r7, 8 // r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) st8 [loc1]=r5, 8 // b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mov r4=b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) st8 [in0]=r8, 8 // r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) st8 [loc1]=r4, 8 // b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mov r5=b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) st8 [in0]=r9, 8 // r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) st8 [loc1]=r5, 8 // b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mov r4=b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) st8 [in0]=r10, 8 // r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) st8 [loc1]=r5, 8 // b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mov r5=b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) st8 [in0]=r11, 8 // r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) st8 [loc1]=r5, 8 // b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mov r4=b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) st8 [in0]=r12, 8 // r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) st8 [loc1]=r4, 8 // ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) mov r5=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) st8 [in0]=r13, 8 // r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) extr.u r5=r5, 0, 38 // ar.pfs.pfm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mov r4=r0 // user mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) st8 [in0]=r14, 8 // r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) st8 [loc1]=r5, 8 // cfm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) st8 [in0]=r15, 8 // r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) st8 [loc1]=r4, 8 // user mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mov r5=ar.rsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) st8 [in0]=r16, 8 // r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) st8 [loc1]=r5, 8 // ar.rsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mov r4=ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) st8 [in0]=r17, 8 // r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) st8 [loc1]=r4, 8 // ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mov r5=ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) st8 [in0]=r18, 8 // r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) st8 [loc1]=r5, 8 // ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mov r4=ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) st8 [in0]=r19, 8 // r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st8 [loc1]=r4, 8 // ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mov r5=ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) st8 [in0]=r20, 8 // r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) st8 [loc1]=r5, 8 // ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mov r4=ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) st8 [in0]=r21, 8 // r21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) st8 [loc1]=r4, 8 // ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mov r5 = ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) st8 [in0]=r22, 8 // r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) st8 [loc1]=r5, 8 // ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mov r4 = ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) st8 [in0]=r23, 8 // r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) st8 [loc1]=r4, 8 // unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mov r5 = ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) st8 [in0]=r24, 8 // r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) st8 [loc1]=r5, 8 // fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mov r4 = ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) st8 [in0]=r25, 8 // r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st8 [loc1]=r4, 8 // ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mov r5 = ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) st8 [in0]=r26, 8 // r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) st8 [loc1]=r5, 8 // ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mov r4 = ar.ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) st8 [in0]=r27, 8 // r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) st8 [loc1]=r4, 8 // ar.ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mov r5 = ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) st8 [in0]=r28, 8 // r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) st8 [loc1]=r5, 8 // ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mov r4 = ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) st8 [in0]=r29, 8 // r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) st8 [loc1]=r4, 8 // ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) st8 [in0]=r30, 8 // r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) st8 [in0]=r31, 8 // r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) mov ar.pfs=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) END(ia64_dump_cpu_regs)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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