^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains the McKinley PMU register description tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * and pmc checker used by perfmon.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2002-2003 Hewlett Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Stephane Eranian <eranian@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* pmc0 */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* pmc1 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* pmc2 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* pmc3 */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* pmc4 */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* pmc5 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* pmc6 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* pmc7 */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* pmc8 */ { PFM_REG_CONFIG , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* pmc9 */ { PFM_REG_CONFIG , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* pmc10 */ { PFM_REG_MONITOR , 4, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* pmc11 */ { PFM_REG_MONITOR , 6, 0x0UL, 0x30f01cf, NULL, pfm_mck_pmc_check, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* pmc13 */ { PFM_REG_CONFIG , 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* pmc14 */ { PFM_REG_CONFIG , 0, 0x0db60db60db60db6UL, 0x2492UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* pmc15 */ { PFM_REG_CONFIG , 0, 0x00000000fffffff0UL, 0xfUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* pmd0 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* pmd1 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* pmd2 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* pmd3 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* pmd4 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pmd5 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* pmd6 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* pmd7 */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* pmd8 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* pmd9 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* pmd10 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pmd11 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* pmd12 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* pmd13 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* pmd14 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* pmd15 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* pmd16 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* pmd17 */ { PFM_REG_BUFFER , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) { PFM_REG_END , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * PMC reserved fields must have their power-up values preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pfm_mck_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned long tmp1, tmp2, ival = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* remove reserved areas from user value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) tmp1 = ival & PMC_RSVD_MASK(cnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* get reserved fields values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *val = tmp1 | tmp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * task can be NULL if the context is unloaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret = 0, check_case1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned long val8 = 0, val14 = 0, val13 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int is_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* first preserve the reserved fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) pfm_mck_reserved(cnum, val, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* sanitfy check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ctx == NULL) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * we must clear the debug registers if pmc13 has a value which enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * memory pipeline event constraints. In this case we need to clear the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * the debug registers if they have not yet been accessed. This is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * to avoid picking stale state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * PMC13 is "active" if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * one of the pmc13.cfg_dbrpXX field is different from 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * at the corresponding pmc13.ena_dbrpXX is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (cnum == 13 && is_loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* don't mix debug with perfmon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * a count of 0 will mark the debug registers as in use and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * ensure that they are properly cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * we must clear the (instruction) debug registers if any pmc14.ibrpX bit is enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * before they are (fl_using_dbreg==0) to avoid picking up stale information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (cnum == 14 && is_loaded && ((*val & 0x2222UL) != 0x2222UL) && ctx->ctx_fl_using_dbreg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* don't mix debug with perfmon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * a count of 0 will mark the debug registers as in use and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * ensure that they are properly cleared.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) switch(cnum) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case 4: *val |= 1UL << 23; /* force power enable bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case 8: val8 = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) val13 = ctx->ctx_pmcs[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) val14 = ctx->ctx_pmcs[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) check_case1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) case 13: val8 = ctx->ctx_pmcs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) val13 = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) val14 = ctx->ctx_pmcs[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) check_case1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case 14: val8 = ctx->ctx_pmcs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val13 = ctx->ctx_pmcs[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val14 = *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) check_case1 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* check illegal configuration which can produce inconsistencies in tagging
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * i-side events in L1D and L2 caches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (check_case1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ret = ((val13 >> 45) & 0xf) == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) && ((val8 & 0x1) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) && ((((val14>>1) & 0x3) == 0x2 || ((val14>>1) & 0x3) == 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ||(((val14>>4) & 0x3) == 0x2 || ((val14>>4) & 0x3) == 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret) DPRINT((KERN_DEBUG "perfmon: failure check_case1\n"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret ? -EINVAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static pmu_config_t pmu_conf_mck={
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .pmu_name = "Itanium 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .pmu_family = 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .flags = PFM_PMU_IRQ_RESEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .ovfl_val = (1UL << 47) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .pmd_desc = pfm_mck_pmd_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .pmc_desc = pfm_mck_pmc_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .num_ibrs = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .num_dbrs = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .use_rr_dbregs = 1 /* debug register are use for range restrictions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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