^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Instruction-patching support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/patch.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * This was adapted from code written by Tony Luck:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * The 64-bit value in a "movl reg=value" is scattered between the two words of the bundle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 6 6 5 4 3 2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 3210987654321098765432109876543210987654321098765432109876543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * ABBBBBBBBBBBBBBBBBBBBBBBCCCCCCCCCCCCCCCCCCDEEEEEFFFFFFFFFGGGGGGG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * CCCCCCCCCCCCCCCCCCxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * xxxxAFFFFFFFFFEEEEEDxGGGGGGGxxxxxxxxxxxxxBBBBBBBBBBBBBBBBBBBBBBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) get_imm64 (u64 insn_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u64 *p = (u64 *) (insn_addr & -16); /* mask out slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return ( (p[1] & 0x0800000000000000UL) << 4) | /*A*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) ((p[1] & 0x00000000007fffffUL) << 40) | /*B*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ((p[0] & 0xffffc00000000000UL) >> 24) | /*C*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ((p[1] & 0x0000100000000000UL) >> 23) | /*D*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ((p[1] & 0x0003e00000000000UL) >> 29) | /*E*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ((p[1] & 0x07fc000000000000UL) >> 43) | /*F*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) ((p[1] & 0x000007f000000000UL) >> 36); /*G*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Patch instruction with "val" where "mask" has 1 bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) ia64_patch (u64 insn_addr, u64 mask, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 m0, m1, v0, v1, b0, b1, *b = (u64 *) (insn_addr & -16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # define insn_mask ((1UL << 41) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) unsigned long shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) b0 = b[0]; b1 = b[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) shift = 5 + 41 * (insn_addr % 16); /* 5 bits of template, then 3 x 41-bit instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (shift >= 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) m1 = mask << (shift - 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) v1 = val << (shift - 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) m0 = mask << shift; m1 = mask >> (64 - shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) v0 = val << shift; v1 = val >> (64 - shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) b[0] = (b0 & ~m0) | (v0 & m0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) b[1] = (b1 & ~m1) | (v1 & m1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ia64_patch_imm64 (u64 insn_addr, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* The assembler may generate offset pointing to either slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) or slot 2 for a long (2-slot) instruction, occupying slots 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) and 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) insn_addr &= -16UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ia64_patch(insn_addr + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x01fffefe000UL, ( ((val & 0x8000000000000000UL) >> 27) /* bit 63 -> 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) | ((val & 0x0000000000200000UL) << 0) /* bit 21 -> 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) | ((val & 0x00000000001f0000UL) << 6) /* bit 16 -> 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) | ((val & 0x000000000000ff80UL) << 20) /* bit 7 -> 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) | ((val & 0x000000000000007fUL) << 13) /* bit 0 -> 13 */));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ia64_patch(insn_addr + 1, 0x1ffffffffffUL, val >> 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ia64_patch_imm60 (u64 insn_addr, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* The assembler may generate offset pointing to either slot 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) or slot 2 for a long (2-slot) instruction, occupying slots 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) and 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) insn_addr &= -16UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ia64_patch(insn_addr + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x011ffffe000UL, ( ((val & 0x0800000000000000UL) >> 23) /* bit 59 -> 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) | ((val & 0x00000000000fffffUL) << 13) /* bit 0 -> 13 */));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ia64_patch(insn_addr + 1, 0x1fffffffffcUL, val >> 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * We need sometimes to load the physical address of a kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * object. Often we can convert the virtual address to physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * at execution time, but sometimes (either for performance reasons
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * or during error recovery) we cannot to this. Patch the marked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * bundles to load the physical address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ia64_patch_vtop (unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) s32 *offp = (s32 *) start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u64 ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) while (offp < (s32 *) end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ip = (u64) offp + *offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* replace virtual address with corresponding physical address: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ia64_patch_imm64(ip, ia64_tpa(get_imm64(ip)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ia64_fc((void *) ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * Disable the RSE workaround by turning the conditional branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * that we tagged in each place the workaround was used into an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * unconditional branch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ia64_patch_rse (unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) s32 *offp = (s32 *) start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u64 ip, *b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) while (offp < (s32 *) end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ip = (u64) offp + *offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) b = (u64 *)(ip & -16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) b[1] &= ~0xf800000L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ia64_fc((void *) ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ia64_patch_mckinley_e9 (unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int first_time = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int need_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) s32 *offp = (s32 *) start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 *wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) need_workaround = (local_cpu_data->family == 0x1f && local_cpu_data->model == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (first_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) first_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (need_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) printk(KERN_INFO "Leaving McKinley Errata 9 workaround enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (need_workaround)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) while (offp < (s32 *) end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) wp = (u64 *) ia64_imva((char *) offp + *offp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) wp[0] = 0x0000000100000011UL; /* nop.m 0; nop.i 0; br.ret.sptk.many b6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) wp[1] = 0x0084006880000200UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) wp[2] = 0x0000000100000000UL; /* nop.m 0; nop.i 0; nop.i 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wp[3] = 0x0004000000000200UL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ia64_fc(wp); ia64_fc(wp + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) patch_fsyscall_table (unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) extern unsigned long fsyscall_table[NR_syscalls];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) s32 *offp = (s32 *) start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u64 ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) while (offp < (s32 *) end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ip = (u64) ia64_imva((char *) offp + *offp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ia64_patch_imm64(ip, (u64) fsyscall_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ia64_fc((void *) ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) patch_brl_fsys_bubble_down (unsigned long start, unsigned long end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) extern char fsys_bubble_down[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) s32 *offp = (s32 *) start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u64 ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) while (offp < (s32 *) end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ip = (u64) offp + *offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ia64_patch_imm60((u64) ia64_imva((void *) ip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) (u64) (fsys_bubble_down - (ip & -16)) / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ia64_fc((void *) ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) void __init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ia64_patch_gate (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) # define START(name) ((unsigned long) __start_gate_##name##_patchlist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) # define END(name) ((unsigned long)__end_gate_##name##_patchlist)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) patch_fsyscall_table(START(fsyscall), END(fsyscall));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) patch_brl_fsys_bubble_down(START(brl_fsys_bubble_down), END(brl_fsys_bubble_down));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ia64_patch_vtop(START(vtop), END(vtop));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ia64_patch_mckinley_e9(START(mckinley_e9), END(mckinley_e9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void ia64_patch_phys_stack_reg(unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) s32 * offp = (s32 *) __start___phys_stack_reg_patchlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) s32 * end = (s32 *) __end___phys_stack_reg_patchlist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u64 ip, mask, imm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* see instruction format A4: adds r1 = imm13, r3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mask = (0x3fUL << 27) | (0x7f << 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) imm = (((val >> 7) & 0x3f) << 27) | (val & 0x7f) << 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) while (offp < end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ip = (u64) offp + *offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ia64_patch(ip, mask, imm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ia64_fc((void *)ip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ++offp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) ia64_sync_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ia64_srlz_i();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags