^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include "entry.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <asm/native/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* read ar.itc in advance, and use it before leaving bank 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ACCOUNT_GET_STAMP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) (pUStk) mov.m r20=ar.itc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ACCOUNT_SYS_ENTER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) (pUStk) br.call.spnt rp=account_sys_enter \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ACCOUNT_GET_STAMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ACCOUNT_SYS_ENTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .section ".data..patch.rse", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * the minimum state necessary that allows us to turn psr.ic back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Assumed state upon entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * psr.ic: off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * r31: contains saved predicates (pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Upon exit, the state is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * psr.ic: off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * r2 = points to &pt_regs.r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * r8 = contents of ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * r9 = contents of ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * r10 = contents of ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * r11 = FPSR_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * r12 = kernel sp (kernel virtual address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * r13 = points to current task_struct (kernel virtual address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * p15 = TRUE if psr.i is set in cr.ipsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * preserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Note that psr.ic is NOT turned on by this macro. This is so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * we can pass interruption state as arguments to a handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IA64_NATIVE_DO_SAVE_MIN(__COVER,SAVE_IFS,EXTRA,WORKAROUND) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mov r16=IA64_KR(CURRENT); /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) mov r27=ar.rsc; /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mov r20=r1; /* A */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mov r25=ar.unat; /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MOV_FROM_IPSR(p0,r29); /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mov r26=ar.pfs; /* I */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MOV_FROM_IIP(r28); /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mov r21=ar.fpsr; /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) __COVER; /* B;; (or nothing) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ld1 r17=[r16]; /* load current->thread.on_ustack flag */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) st1 [r16]=r0; /* clear current->thread.on_ustack flag */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) adds r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* switch from user to kernel RBS: */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) invala; /* M */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) SAVE_IFS; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) cmp.eq pKStk,pUStk=r0,r17; /* are we in kernel mode already? */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) (pUStk) mov ar.rsc=0; /* set enforced lazy mode, pl 0, little-endian, loadrs=0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) (pUStk) mov.m r24=ar.rnat; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) (pUStk) addl r22=IA64_RBS_OFFSET,r1; /* compute base of RBS */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (pKStk) mov r1=sp; /* get sp */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (pUStk) lfetch.fault.excl.nt1 [r22]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (pUStk) addl r1=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (pUStk) mov r23=ar.bspstore; /* save ar.bspstore */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (pUStk) mov ar.bspstore=r22; /* switch to kernel RBS */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (pKStk) addl r1=-IA64_PT_REGS_SIZE,r1; /* if in kernel mode, use sp (r12) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (pUStk) mov r18=ar.bsp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (pUStk) mov ar.rsc=0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) adds r17=2*L1_CACHE_BYTES,r1; /* really: biggest cache-line size */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) adds r16=PT(CR_IPSR),r1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) st8 [r16]=r29; /* save cr.ipsr */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) lfetch.fault.excl.nt1 [r17]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) tbit.nz p15,p0=r29,IA64_PSR_I_BIT; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mov r29=b0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) WORKAROUND; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) adds r16=PT(R8),r1; /* initialize first base pointer */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) adds r17=PT(R9),r1; /* initialize second base pointer */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) (pKStk) mov r18=r0; /* make sure r18 isn't NaT */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .mem.offset 0,0; st8.spill [r16]=r8,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .mem.offset 8,0; st8.spill [r17]=r9,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .mem.offset 0,0; st8.spill [r16]=r10,24; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .mem.offset 8,0; st8.spill [r17]=r11,24; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) st8 [r16]=r28,16; /* save cr.iip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) st8 [r17]=r30,16; /* save cr.ifs */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) (pUStk) sub r18=r18,r22; /* r18=RSE.ndirty*8 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mov r8=ar.ccv; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) mov r9=ar.csd; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) mov r10=ar.ssd; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) movl r11=FPSR_DEFAULT; /* L-unit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) st8 [r16]=r25,16; /* save ar.unat */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) st8 [r17]=r26,16; /* save ar.pfs */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) shl r18=r18,16; /* compute ar.rsc to be used for "loadrs" */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) st8 [r16]=r27,16; /* save ar.rsc */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (pUStk) st8 [r17]=r24,16; /* save ar.rnat */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (pKStk) adds r17=16,r17; /* skip over ar_rnat field */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ;; /* avoid RAW on r16 & r17 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) (pUStk) st8 [r16]=r23,16; /* save ar.bspstore */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) st8 [r17]=r31,16; /* save predicates */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) (pKStk) adds r16=16,r16; /* skip over ar_bspstore field */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) st8 [r16]=r29,16; /* save b0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) st8 [r17]=r18,16; /* save ar.rsc value for "loadrs" */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) cmp.eq pNonSys,pSys=r0,r0 /* initialize pSys=0, pNonSys=1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .mem.offset 0,0; st8.spill [r16]=r20,16; /* save original r1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .mem.offset 8,0; st8.spill [r17]=r12,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) adds r12=-16,r1; /* switch to kernel memory stack (with 16 bytes of scratch) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .mem.offset 0,0; st8.spill [r16]=r13,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .mem.offset 8,0; st8.spill [r17]=r21,16; /* save ar.fpsr */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) mov r13=IA64_KR(CURRENT); /* establish `current' */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .mem.offset 0,0; st8.spill [r16]=r15,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mem.offset 8,0; st8.spill [r17]=r14,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .mem.offset 0,0; st8.spill [r16]=r2,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .mem.offset 8,0; st8.spill [r17]=r3,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) ACCOUNT_GET_STAMP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) adds r2=IA64_PT_REGS_R16_OFFSET,r1; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXTRA; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) movl r1=__gp; /* establish kernel global pointer */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ACCOUNT_SYS_ENTER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bsw.1; /* switch back to bank 1 (must be last in insn group) */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * SAVE_REST saves the remainder of pt_regs (with psr.ic on).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * Assumed state upon entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * psr.ic: on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * r2: points to &pt_regs.r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * r3: points to &pt_regs.r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * r8: contents of ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * r9: contents of ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * r10: contents of ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * r11: FPSR_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SAVE_REST \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .mem.offset 0,0; st8.spill [r2]=r16,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .mem.offset 8,0; st8.spill [r3]=r17,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .mem.offset 0,0; st8.spill [r2]=r18,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .mem.offset 8,0; st8.spill [r3]=r19,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .mem.offset 0,0; st8.spill [r2]=r20,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .mem.offset 8,0; st8.spill [r3]=r21,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mov r18=b6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .mem.offset 0,0; st8.spill [r2]=r22,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .mem.offset 8,0; st8.spill [r3]=r23,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) mov r19=b7; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .mem.offset 0,0; st8.spill [r2]=r24,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .mem.offset 8,0; st8.spill [r3]=r25,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .mem.offset 0,0; st8.spill [r2]=r26,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .mem.offset 8,0; st8.spill [r3]=r27,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .mem.offset 0,0; st8.spill [r2]=r28,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .mem.offset 8,0; st8.spill [r3]=r29,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .mem.offset 0,0; st8.spill [r2]=r30,16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .mem.offset 8,0; st8.spill [r3]=r31,32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mov ar.fpsr=r11; /* M-unit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) st8 [r2]=r8,8; /* ar.ccv */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) adds r24=PT(B6)-PT(F7),r3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) stf.spill [r2]=f6,32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) stf.spill [r3]=f7,32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) stf.spill [r2]=f8,32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) stf.spill [r3]=f9,32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) stf.spill [r2]=f10; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) stf.spill [r3]=f11; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) adds r25=PT(B7)-PT(F11),r3; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) st8 [r24]=r18,16; /* b6 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) st8 [r25]=r19,16; /* b7 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) st8 [r24]=r9; /* ar.csd */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) st8 [r25]=r10; /* ar.ssd */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define RSE_WORKAROUND \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (pUStk) extr.u r17=r18,3,6; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (pUStk) sub r16=r18,r22; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [1:](pKStk) br.cond.sptk.many 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .xdata4 ".data..patch.rse",1b-. \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cmp.ge p6,p7 = 33,r17; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (p6) mov r17=0x310; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) (p7) mov r17=0x308; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) cmp.leu p1,p0=r16,r17; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (p1) br.cond.sptk.many 1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dep.z r17=r26,0,62; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) movl r16=2f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mov ar.pfs=r17; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dep r27=r0,r27,16,14; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mov b0=r16; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) br.ret.sptk b0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 2: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mov ar.rsc=r0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) flushrs; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mov ar.bspstore=r22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mov r18=ar.bsp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .pred.rel "mutex", pKStk, pUStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SAVE_MIN_WITH_COVER DO_SAVE_MIN(COVER, mov r30=cr.ifs, , RSE_WORKAROUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SAVE_MIN_WITH_COVER_R19 DO_SAVE_MIN(COVER, mov r30=cr.ifs, mov r15=r19, RSE_WORKAROUND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SAVE_MIN DO_SAVE_MIN( , mov r30=r0, , )
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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