^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Here is where the ball gets rolling as far as the kernel is concerned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * When control is transferred to _start, the bootload has already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * loaded us to the correct address. All that's left to do here is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * to set up the kernel's global pointer and jump to the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * entry point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Stephane Eranian <eranian@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1999 VA Linux Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1999 Intel Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Support for CPU Hotplug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/kregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/pal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <asm/mca_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SAL_PSR_BITS_TO_SET \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SAVE_FROM_REG(src, ptr, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mov dest=src;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) st8 [ptr]=dest,0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RESTORE_REG(reg, ptr, _tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ld8 _tmp=[ptr],0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) mov reg=_tmp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) mov ar.lc=IA64_NUM_DBG_REGS-1;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mov _idx=0;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) SAVE_FROM_REG(_breg[_idx], ptr, _dest);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) add _idx=1,_idx;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) br.cloop.sptk.many 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mov ar.lc=IA64_NUM_DBG_REGS-1;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mov _idx=0;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) _lbl: RESTORE_REG(_breg[_idx], ptr, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) add _idx=1, _idx;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) br.cloop.sptk.many _lbl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAVE_ONE_RR(num, _reg, _tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) movl _tmp=(num<<61);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mov _reg=rr[_tmp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) SAVE_ONE_RR(0,_r0, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SAVE_ONE_RR(1,_r1, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) SAVE_ONE_RR(2,_r2, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) SAVE_ONE_RR(3,_r3, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) SAVE_ONE_RR(4,_r4, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) SAVE_ONE_RR(5,_r5, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) SAVE_ONE_RR(6,_r6, _tmp);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) SAVE_ONE_RR(7,_r7, _tmp);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) st8 [ptr]=_r0, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) st8 [ptr]=_r1, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) st8 [ptr]=_r2, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) st8 [ptr]=_r3, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) st8 [ptr]=_r4, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) st8 [ptr]=_r5, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) st8 [ptr]=_r6, 8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) st8 [ptr]=_r7, 8;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mov ar.lc=0x08-1;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) movl _idx1=0x00;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) RestRR: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) dep.z _idx2=_idx1,61,3;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ld8 _tmp=[ptr],8;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mov rr[_idx2]=_tmp;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) srlz.d;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) add _idx1=1,_idx1;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) br.cloop.sptk.few RestRR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) movl reg1=sal_state_for_booting_cpu;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ld8 reg2=[reg1];;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * Adjust region registers saved before starting to save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * break regs and rest of the states that need to be preserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) SAVE_FROM_REG(b0,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) SAVE_FROM_REG(b1,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) SAVE_FROM_REG(b2,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) SAVE_FROM_REG(b3,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) SAVE_FROM_REG(b4,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) SAVE_FROM_REG(b5,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) st8 [_reg1]=r1,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) st8 [_reg1]=r12,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) st8 [_reg1]=r13,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SAVE_FROM_REG(ar.pfs,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SAVE_FROM_REG(ar.rnat,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) SAVE_FROM_REG(ar.unat,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) SAVE_FROM_REG(cr.dcr,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) SAVE_FROM_REG(cr.iva,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) SAVE_FROM_REG(cr.pta,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) SAVE_FROM_REG(cr.itv,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) SAVE_FROM_REG(cr.pmv,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) st8 [_reg1]=r4,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) st8 [_reg1]=r5,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) st8 [_reg1]=r6,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) st8 [_reg1]=r7,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) st8 [_reg1]=_pred,0x08;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SAVE_FROM_REG(ar.lc, _reg1, _reg2);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) stf.spill.nta [_reg1]=f2,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) stf.spill.nta [_reg1]=f3,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) stf.spill.nta [_reg1]=f4,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) stf.spill.nta [_reg1]=f5,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) stf.spill.nta [_reg1]=f16,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) stf.spill.nta [_reg1]=f17,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) stf.spill.nta [_reg1]=f18,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) stf.spill.nta [_reg1]=f19,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) stf.spill.nta [_reg1]=f20,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) stf.spill.nta [_reg1]=f21,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) stf.spill.nta [_reg1]=f22,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) stf.spill.nta [_reg1]=f23,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) stf.spill.nta [_reg1]=f24,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) stf.spill.nta [_reg1]=f25,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) stf.spill.nta [_reg1]=f26,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) stf.spill.nta [_reg1]=f27,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) stf.spill.nta [_reg1]=f28,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) stf.spill.nta [_reg1]=f29,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) stf.spill.nta [_reg1]=f30,16;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) stf.spill.nta [_reg1]=f31,16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SET_AREA_FOR_BOOTING_CPU(a1, a2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) movl _tmp1=(num << 61);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mov rr[_tmp1]=_tmp2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) __PAGE_ALIGNED_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .global empty_zero_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) EXPORT_DATA_SYMBOL_GPL(empty_zero_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) empty_zero_page:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .skip PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .global swapper_pg_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) swapper_pg_dir:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .skip PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .rodata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) halt_msg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) stringz "Halting kernel\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) __REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .global start_ap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * Start the kernel. When the bootloader passes control to _start(), r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * points to the address of the boot parameter area. Execution reaches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * here in physical mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) GLOBAL_ENTRY(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) start_ap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .save rp, r0 // terminate unwind chain with a NULL rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rsm psr.i | psr.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) flushrs // must be first insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Save the region registers, predicate before they get clobbered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mov r25=pr;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Initialize kernel region registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * rr[0]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * rr[1]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * rr[2]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * rr[3]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * rr[4]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * rr[5]: VHPT enabled, page size = PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * We initialize all of them to prevent inadvertently assuming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * something about the state of address translation early in boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * Now pin mappings into the TLB for kernel text and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) mov r18=KERNEL_TR_PAGE_SHIFT<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) movl r17=KERNEL_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) mov cr.itir=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mov cr.ifa=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mov r16=IA64_TR_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mov r3=ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) movl r18=PAGE_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) or r18=r2,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) itr.i itr[r16]=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) itr.d dtr[r16]=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * Switch into virtual mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) |IA64_PSR_DI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) mov cr.ipsr=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) movl r17=1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mov cr.iip=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) mov cr.ifs=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 1: // now we are in virtual mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SET_AREA_FOR_BOOTING_CPU(r2, r16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) // set IVT entry point---can't access I/O ports without it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) movl r3=ia64_ivt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mov cr.iva=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) movl r2=FPSR_DEFAULT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) movl gp=__gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mov ar.fpsr=r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define isAP p2 // are we an Application Processor?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define isBP p3 // are we the Bootstrap Processor?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Find the init_task for the currently booting CPU. At poweron, and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * UP mode, task_for_booting_cpu is NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) movl r3=task_for_booting_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ld8 r3=[r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) movl r2=init_task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) cmp.eq isBP,isAP=r3,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (isAP) mov r2=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) movl r2=init_task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) cmp.eq isBP,isAP=r0,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tpa r3=r2 // r3 == phys addr of task struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mov r16=-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (isBP) br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) // load mapping for stack (virtaddr in r2, physaddr in r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) rsm psr.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) movl r17=PAGE_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) srlz.d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dep r18=0,r3,0,12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) or r18=r17,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dep r2=-1,r3,61,3 // IMVA of task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mov r17=rr[r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) shr.u r16=r3,IA64_GRANULE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dep r17=0,r17,8,24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mov cr.itir=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) mov cr.ifa=r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mov r19=IA64_TR_CURRENT_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) itr.d dtr[r19]=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ssm psr.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) srlz.d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .load_current:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) // load the "current" pointer (r13) and ar.k6 with the current task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) mov IA64_KR(CURRENT)=r2 // virtual address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mov IA64_KR(CURRENT_STACK)=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) mov r13=r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * Reserve space at the top of the stack for "struct pt_regs". Kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * threads don't store interesting values in that structure, but the space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * still needs to be there because time-critical stuff such as the context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * switching can be implemented more efficiently (for example, __switch_to()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * always sets the psr.dfh bit of the task it is switching to).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) addl r2=IA64_RBS_OFFSET,r2 // initialize the RSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mov ar.rsc=0 // place RSE in enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) loadrs // clear the dirty partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) movl r19=__phys_per_cpu_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mov r18=PERCPU_PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #ifndef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) add r19=r19,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) (isAP) br.few 2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) movl r20=__cpu0_per_cpu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) shr.u r18=r18,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ld8 r21=[r19],8;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) st8[r20]=r21,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) adds r18=-1,r18;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cmp4.lt p7,p6=0,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) (p7) br.cond.dptk.few 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) mov r19=r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tpa r19=r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .pred.rel.mutex isBP,isAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) (isBP) mov IA64_KR(PER_CPU_DATA)=r19 // per-CPU base for cpu0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (isAP) mov IA64_KR(PER_CPU_DATA)=r0 // clear physical per-CPU base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mov ar.bspstore=r2 // establish the new RSE stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mov ar.rsc=0x3 // place RSE in eager mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) (isBP) dep r28=-1,r28,61,3 // make address virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) (isBP) movl r2=ia64_boot_param
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) (isBP) st8 [r2]=r28 // save the address of the boot param area passed by the bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) (isAP) br.call.sptk.many rp=start_secondary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .ret0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) (isAP) br.cond.sptk self
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) // This is executed by the bootstrap processor (bsp) only:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #ifdef CONFIG_IA64_FW_EMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) // initialize PAL & SAL emulator:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) br.call.sptk.many rp=sys_fw_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ret1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) br.call.sptk.many rp=start_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .ret2: addl r3=@ltoff(halt_msg),gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) alloc r2=ar.pfs,8,0,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ld8 out0=[r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) br.call.sptk.many b0=console_print
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) self: hint @pause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) br.sptk.many self // endless loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) END(_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GLOBAL_ENTRY(ia64_save_debug_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) alloc r16=ar.pfs,1,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mov r20=ar.lc // preserve ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mov ar.lc=IA64_NUM_DBG_REGS-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mov r18=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) add r19=IA64_NUM_DBG_REGS*8,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 1: mov r16=dbr[r18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) srlz.d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) mov r17=ibr[r18]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) add r18=1,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) st8.nta [in0]=r16,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) st8.nta [r19]=r17,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) br.cloop.sptk.many 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mov ar.lc=r20 // restore ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) END(ia64_save_debug_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GLOBAL_ENTRY(ia64_load_debug_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) alloc r16=ar.pfs,1,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) lfetch.nta [in0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) mov r20=ar.lc // preserve ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) add r19=IA64_NUM_DBG_REGS*8,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mov ar.lc=IA64_NUM_DBG_REGS-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) mov r18=-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 1: ld8.nta r16=[in0],8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ld8.nta r17=[r19],8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) add r18=1,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) mov dbr[r18]=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) srlz.d // Errata 132 (NoFix status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mov ibr[r18]=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) br.cloop.sptk.many 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mov ar.lc=r20 // restore ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) END(ia64_load_debug_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) GLOBAL_ENTRY(__ia64_save_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) alloc r2=ar.pfs,1,4,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) adds loc0=96*16-16,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) adds loc1=96*16-16-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) stf.spill.nta [loc0]=f127,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) stf.spill.nta [loc1]=f119,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) stf.spill.nta [loc0]=f111,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) stf.spill.nta [loc1]=f103,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) stf.spill.nta [loc0]=f95,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) stf.spill.nta [loc1]=f87,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) stf.spill.nta [loc0]=f79,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) stf.spill.nta [loc1]=f71,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) stf.spill.nta [loc0]=f63,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) stf.spill.nta [loc1]=f55,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) adds loc2=96*16-32,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) stf.spill.nta [loc0]=f47,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) stf.spill.nta [loc1]=f39,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) adds loc3=96*16-32-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) stf.spill.nta [loc2]=f126,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) stf.spill.nta [loc3]=f118,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) stf.spill.nta [loc2]=f110,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) stf.spill.nta [loc3]=f102,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) stf.spill.nta [loc2]=f94,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) stf.spill.nta [loc3]=f86,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) stf.spill.nta [loc2]=f78,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) stf.spill.nta [loc3]=f70,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) stf.spill.nta [loc2]=f62,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) stf.spill.nta [loc3]=f54,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) adds loc0=96*16-48,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) stf.spill.nta [loc2]=f46,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) stf.spill.nta [loc3]=f38,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) adds loc1=96*16-48-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) stf.spill.nta [loc0]=f125,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) stf.spill.nta [loc1]=f117,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) stf.spill.nta [loc0]=f109,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) stf.spill.nta [loc1]=f101,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) stf.spill.nta [loc0]=f93,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) stf.spill.nta [loc1]=f85,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) stf.spill.nta [loc0]=f77,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) stf.spill.nta [loc1]=f69,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) stf.spill.nta [loc0]=f61,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) stf.spill.nta [loc1]=f53,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) adds loc2=96*16-64,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) stf.spill.nta [loc0]=f45,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stf.spill.nta [loc1]=f37,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) adds loc3=96*16-64-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) stf.spill.nta [loc2]=f124,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) stf.spill.nta [loc3]=f116,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) stf.spill.nta [loc2]=f108,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) stf.spill.nta [loc3]=f100,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) stf.spill.nta [loc2]=f92,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) stf.spill.nta [loc3]=f84,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) stf.spill.nta [loc2]=f76,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) stf.spill.nta [loc3]=f68,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) stf.spill.nta [loc2]=f60,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) stf.spill.nta [loc3]=f52,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) adds loc0=96*16-80,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) stf.spill.nta [loc2]=f44,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) stf.spill.nta [loc3]=f36,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) adds loc1=96*16-80-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) stf.spill.nta [loc0]=f123,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) stf.spill.nta [loc1]=f115,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) stf.spill.nta [loc0]=f107,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) stf.spill.nta [loc1]=f99,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) stf.spill.nta [loc0]=f91,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) stf.spill.nta [loc1]=f83,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) stf.spill.nta [loc0]=f75,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) stf.spill.nta [loc1]=f67,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) stf.spill.nta [loc0]=f59,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) stf.spill.nta [loc1]=f51,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) adds loc2=96*16-96,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) stf.spill.nta [loc0]=f43,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) stf.spill.nta [loc1]=f35,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) adds loc3=96*16-96-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) stf.spill.nta [loc2]=f122,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) stf.spill.nta [loc3]=f114,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) stf.spill.nta [loc2]=f106,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) stf.spill.nta [loc3]=f98,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) stf.spill.nta [loc2]=f90,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) stf.spill.nta [loc3]=f82,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) stf.spill.nta [loc2]=f74,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) stf.spill.nta [loc3]=f66,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) stf.spill.nta [loc2]=f58,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) stf.spill.nta [loc3]=f50,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) adds loc0=96*16-112,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) stf.spill.nta [loc2]=f42,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) stf.spill.nta [loc3]=f34,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) adds loc1=96*16-112-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) stf.spill.nta [loc0]=f121,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) stf.spill.nta [loc1]=f113,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) stf.spill.nta [loc0]=f105,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) stf.spill.nta [loc1]=f97,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) stf.spill.nta [loc0]=f89,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) stf.spill.nta [loc1]=f81,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) stf.spill.nta [loc0]=f73,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) stf.spill.nta [loc1]=f65,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) stf.spill.nta [loc0]=f57,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) stf.spill.nta [loc1]=f49,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) adds loc2=96*16-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) stf.spill.nta [loc0]=f41,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) stf.spill.nta [loc1]=f33,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) adds loc3=96*16-128-128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) stf.spill.nta [loc2]=f120,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) stf.spill.nta [loc3]=f112,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) stf.spill.nta [loc2]=f104,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) stf.spill.nta [loc3]=f96,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) stf.spill.nta [loc2]=f88,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) stf.spill.nta [loc3]=f80,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) stf.spill.nta [loc2]=f72,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) stf.spill.nta [loc3]=f64,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) stf.spill.nta [loc2]=f56,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) stf.spill.nta [loc3]=f48,-256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) stf.spill.nta [loc2]=f40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) stf.spill.nta [loc3]=f32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) END(__ia64_save_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GLOBAL_ENTRY(__ia64_load_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) alloc r2=ar.pfs,1,2,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) adds r3=128,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) adds r14=256,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) adds r15=384,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mov loc0=512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) mov loc1=-1024+16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ldf.fill.nta f32=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ldf.fill.nta f40=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ldf.fill.nta f48=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ldf.fill.nta f56=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ldf.fill.nta f64=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ldf.fill.nta f72=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ldf.fill.nta f80=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ldf.fill.nta f88=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ldf.fill.nta f96=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ldf.fill.nta f104=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ldf.fill.nta f112=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ldf.fill.nta f120=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ldf.fill.nta f33=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) ldf.fill.nta f41=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ldf.fill.nta f49=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ldf.fill.nta f57=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ldf.fill.nta f65=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ldf.fill.nta f73=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) ldf.fill.nta f81=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ldf.fill.nta f89=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ldf.fill.nta f97=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ldf.fill.nta f105=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ldf.fill.nta f113=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ldf.fill.nta f121=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ldf.fill.nta f34=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ldf.fill.nta f42=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ldf.fill.nta f50=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ldf.fill.nta f58=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ldf.fill.nta f66=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ldf.fill.nta f74=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ldf.fill.nta f82=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ldf.fill.nta f90=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ldf.fill.nta f98=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ldf.fill.nta f106=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ldf.fill.nta f114=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ldf.fill.nta f122=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ldf.fill.nta f35=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ldf.fill.nta f43=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ldf.fill.nta f51=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ldf.fill.nta f59=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ldf.fill.nta f67=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ldf.fill.nta f75=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ldf.fill.nta f83=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ldf.fill.nta f91=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ldf.fill.nta f99=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ldf.fill.nta f107=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ldf.fill.nta f115=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ldf.fill.nta f123=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ldf.fill.nta f36=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ldf.fill.nta f44=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ldf.fill.nta f52=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ldf.fill.nta f60=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ldf.fill.nta f68=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ldf.fill.nta f76=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ldf.fill.nta f84=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ldf.fill.nta f92=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ldf.fill.nta f100=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ldf.fill.nta f108=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ldf.fill.nta f116=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ldf.fill.nta f124=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ldf.fill.nta f37=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ldf.fill.nta f45=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ldf.fill.nta f53=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ldf.fill.nta f61=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ldf.fill.nta f69=[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ldf.fill.nta f77=[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ldf.fill.nta f85=[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ldf.fill.nta f93=[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ldf.fill.nta f101=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ldf.fill.nta f109=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ldf.fill.nta f117=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ldf.fill.nta f125=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ldf.fill.nta f38 =[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ldf.fill.nta f46 =[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ldf.fill.nta f54 =[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ldf.fill.nta f62 =[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ldf.fill.nta f70 =[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ldf.fill.nta f78 =[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ldf.fill.nta f86 =[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ldf.fill.nta f94 =[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ldf.fill.nta f102=[in0],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ldf.fill.nta f110=[ r3],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ldf.fill.nta f118=[r14],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ldf.fill.nta f126=[r15],loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ldf.fill.nta f39 =[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ldf.fill.nta f47 =[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ldf.fill.nta f55 =[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ldf.fill.nta f63 =[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ldf.fill.nta f71 =[in0],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ldf.fill.nta f79 =[ r3],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ldf.fill.nta f87 =[r14],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ldf.fill.nta f95 =[r15],loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ldf.fill.nta f103=[in0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ldf.fill.nta f111=[ r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ldf.fill.nta f119=[r14]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ldf.fill.nta f127=[r15]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) END(__ia64_load_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) GLOBAL_ENTRY(__ia64_init_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) stf.spill [sp]=f0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mov f32=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) nop.b 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ldfps f33,f34=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ldfps f35,f36=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mov f37=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) setf.s f38=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) setf.s f39=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mov f40=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ldfps f41,f42=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ldfps f43,f44=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mov f45=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) setf.s f46=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) setf.s f47=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) mov f48=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ldfps f49,f50=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ldfps f51,f52=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mov f53=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) setf.s f54=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) setf.s f55=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mov f56=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ldfps f57,f58=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ldfps f59,f60=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mov f61=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) setf.s f62=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) setf.s f63=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mov f64=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ldfps f65,f66=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ldfps f67,f68=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mov f69=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) setf.s f70=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) setf.s f71=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mov f72=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ldfps f73,f74=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ldfps f75,f76=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mov f77=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) setf.s f78=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) setf.s f79=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) mov f80=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ldfps f81,f82=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ldfps f83,f84=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mov f85=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) setf.s f86=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) setf.s f87=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mov f88=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * When the instructions are cached, it would be faster to initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * the remaining registers with simply mov instructions (F-unit).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * This gets the time down to ~29 cycles. However, this would use up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * 33 bundles, whereas continuing with the above pattern yields
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * 10 bundles and ~30 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ldfps f89,f90=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ldfps f91,f92=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) mov f93=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) setf.s f94=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) setf.s f95=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mov f96=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ldfps f97,f98=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ldfps f99,f100=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) mov f101=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) setf.s f102=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) setf.s f103=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) mov f104=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ldfps f105,f106=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ldfps f107,f108=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) mov f109=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) setf.s f110=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) setf.s f111=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mov f112=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ldfps f113,f114=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ldfps f115,f116=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mov f117=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) setf.s f118=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) setf.s f119=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) mov f120=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ldfps f121,f122=[sp] // M0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ldfps f123,f124=[sp] // M1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mov f125=f0 // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) setf.s f126=r0 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) setf.s f127=r0 // M3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) br.ret.sptk.many rp // F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) END(__ia64_init_fpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * Switch execution mode from virtual to physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * Inputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) * r16 = new psr to establish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) * Output:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) * r19 = old virtual address of ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * r20 = old virtual address of sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * Note: RSE must already be in enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) GLOBAL_ENTRY(ia64_switch_mode_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rsm psr.i | psr.ic // disable interrupts and interrupt collection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mov r15=ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) flushrs // must be first insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mov cr.ipsr=r16 // set new PSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) add r3=1f-ia64_switch_mode_phys,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mov r19=ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) mov r20=sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mov r14=rp // get return address into a general register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) // going to physical mode, use tpa to translate virt->phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tpa r17=r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) tpa r3=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) tpa sp=sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) tpa r14=r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) mov r18=ar.rnat // save ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) mov ar.bspstore=r17 // this steps on ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mov cr.iip=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mov cr.ifs=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mov ar.rnat=r18 // restore ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) rfi // must be last insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 1: mov rp=r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) END(ia64_switch_mode_phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) * Switch execution mode from physical to virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * Inputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * r16 = new psr to establish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * r19 = new bspstore to establish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * r20 = new sp to establish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * Note: RSE must already be in enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) GLOBAL_ENTRY(ia64_switch_mode_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) rsm psr.i | psr.ic // disable interrupts and interrupt collection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mov r15=ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) flushrs // must be first insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mov cr.ipsr=r16 // set new PSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) add r3=1f-ia64_switch_mode_virt,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mov r14=rp // get return address into a general register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) // going to virtual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) // - for code addresses, set upper bits of addr to KERNEL_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) // - for stack addresses, copy from input argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) movl r18=KERNEL_START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mov sp=r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) or r3=r3,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) or r14=r14,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) mov r18=ar.rnat // save ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) mov ar.bspstore=r19 // this steps on ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) mov cr.iip=r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) mov cr.ifs=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mov ar.rnat=r18 // restore ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) rfi // must be last insn in group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) 1: mov rp=r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) END(ia64_switch_mode_virt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) GLOBAL_ENTRY(ia64_delay_loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) { nop 0 // work around GAS unwind info generation bug...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .save ar.lc,r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mov r2=ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) mov ar.lc=r32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) // force loop to be 32-byte aligned (GAS bug means we cannot use .align
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) // inside function body without corrupting unwind info).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { nop 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) 1: br.cloop.sptk.few 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) mov ar.lc=r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) END(ia64_delay_loop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Return a CPU-local timestamp in nano-seconds. This timestamp is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * NOT synchronized across CPUs its return value must never be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * compared against the values returned on another CPU. The usage in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * kernel/sched/core.c ensures that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * The return-value of sched_clock() is NOT supposed to wrap-around.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * If it did, it would cause some scheduling hiccups (at the worst).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * that would happen only once every 5+ years.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * The code below basically calculates:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * except that the multiplication and the shift are done with 128-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * intermediate precision so that we can produce a full 64-bit result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GLOBAL_ENTRY(ia64_native_sched_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) mov.m r9=ar.itc // fetch cycle-counter (35 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ldf8 f8=[r8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) setf.sig f9=r9 // certain to stall, so issue it _after_ ldf8...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) getf.sig r8=f10 // (5 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) getf.sig r9=f11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) END(ia64_native_sched_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GLOBAL_ENTRY(cycle_to_nsec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) alloc r16=ar.pfs,1,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ldf8 f8=[r8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) setf.sig f9=r32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) xmpy.lu f10=f9,f8 // calculate low 64 bits of 128-bit product (4 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) xmpy.hu f11=f9,f8 // calculate high 64 bits of 128-bit product
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) getf.sig r8=f10 // (5 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) getf.sig r9=f11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) END(cycle_to_nsec)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #ifdef CONFIG_IA64_BRL_EMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * Assembly routines used by brl_emu.c to set preserved register state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define SET_REG(reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GLOBAL_ENTRY(ia64_set_##reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) alloc r16=ar.pfs,1,0,0,0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mov reg=r32; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) br.ret.sptk.many rp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) END(ia64_set_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SET_REG(b1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SET_REG(b2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SET_REG(b3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) SET_REG(b4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SET_REG(b5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #endif /* CONFIG_IA64_BRL_EMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GLOBAL_ENTRY(ia64_jump_to_sal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) alloc r16=ar.pfs,1,0,0,0;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) rsm psr.i | psr.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) flushrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) srlz.i
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) tpa r25=in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) movl r18=tlb_purge_done;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) DATA_VA_TO_PA(r18);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) mov b1=r18 // Return location
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) movl r18=ia64_do_tlb_purge;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) DATA_VA_TO_PA(r18);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mov b2=r18 // doing tlb_flush work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mov ar.rsc=0 // Put RSE in enforced lazy, LE mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) movl r17=1f;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) DATA_VA_TO_PA(r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mov cr.iip=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) movl r16=SAL_PSR_BITS_TO_SET;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) mov cr.ipsr=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mov cr.ifs=r0;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) rfi;; // note: this unmask MCA/INIT (psr.mc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * Invalidate all TLB data/inst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) br.sptk.many b2;; // jump to tlb purge code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tlb_purge_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) RESTORE_REGION_REGS(r25, r17,r18,r19);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) RESTORE_REG(b0, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) RESTORE_REG(b1, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) RESTORE_REG(b2, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) RESTORE_REG(b3, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) RESTORE_REG(b4, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) RESTORE_REG(b5, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ld8 r1=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ld8 r12=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ld8 r13=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RESTORE_REG(ar.fpsr, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) RESTORE_REG(ar.pfs, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) RESTORE_REG(ar.rnat, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) RESTORE_REG(ar.unat, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) RESTORE_REG(ar.bspstore, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) RESTORE_REG(cr.dcr, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) RESTORE_REG(cr.iva, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) RESTORE_REG(cr.pta, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) srlz.d;; // required not to violate RAW dependency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) RESTORE_REG(cr.itv, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) RESTORE_REG(cr.pmv, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) RESTORE_REG(cr.cmcv, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) RESTORE_REG(cr.lrr0, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) RESTORE_REG(cr.lrr1, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ld8 r4=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ld8 r5=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ld8 r6=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ld8 r7=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ld8 r17=[r25],0x08;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) mov pr=r17,-1;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) RESTORE_REG(ar.lc, r25, r17);;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) * Now Restore floating point regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ldf.fill.nta f2=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) ldf.fill.nta f3=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ldf.fill.nta f4=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ldf.fill.nta f5=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ldf.fill.nta f16=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ldf.fill.nta f17=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ldf.fill.nta f18=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ldf.fill.nta f19=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ldf.fill.nta f20=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ldf.fill.nta f21=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ldf.fill.nta f22=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ldf.fill.nta f23=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ldf.fill.nta f24=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ldf.fill.nta f25=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ldf.fill.nta f26=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ldf.fill.nta f27=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ldf.fill.nta f28=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ldf.fill.nta f29=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ldf.fill.nta f30=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ldf.fill.nta f31=[r25],16;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * Now that we have done all the register restores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * we are now ready for the big DIVE to SAL Land
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ssm psr.ic;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) srlz.d;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) br.ret.sptk.many b0;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) END(ia64_jump_to_sal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #endif /* CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #endif /* CONFIG_SMP */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags