Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file contains the code that gets mapped at the upper end of each task's text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * region.  For now, it contains the signal trampoline code only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 1999-2003 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * 	David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/sigcontext.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/kregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/native/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * We can't easily refer to symbols inside the kernel.  To avoid full runtime relocation,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * complications with the linker (which likes to create PLT stubs for branches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * to targets outside the shared object) and to avoid multi-phase kernel builds, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * simply create minimalistic "patch lists" in special ELF sections.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	.section ".data..patch.fsyscall_table", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	.previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LOAD_FSYSCALL_TABLE(reg)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) [1:]	movl reg=0;					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	.xdata4 ".data..patch.fsyscall_table", 1b-.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	.section ".data..patch.brl_fsys_bubble_down", "a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define BRL_COND_FSYS_BUBBLE_DOWN(pr)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) [1:](pr)brl.cond.sptk 0;				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	;;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	.xdata4 ".data..patch.brl_fsys_bubble_down", 1b-.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) GLOBAL_ENTRY(__kernel_syscall_via_break)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	.prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	.altrp b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	 * Note: for (fast) syscall restart to work, the break instruction must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	 *	 the first one in the bundle addressed by syscall_via_break.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) { .mib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	break 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	br.ret.sptk.many b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) END(__kernel_syscall_via_break)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #	define ARG0_OFF		(16 + IA64_SIGFRAME_ARG0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #	define ARG1_OFF		(16 + IA64_SIGFRAME_ARG1_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #	define ARG2_OFF		(16 + IA64_SIGFRAME_ARG2_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #	define SIGHANDLER_OFF	(16 + IA64_SIGFRAME_HANDLER_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #	define SIGCONTEXT_OFF	(16 + IA64_SIGFRAME_SIGCONTEXT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #	define FLAGS_OFF	IA64_SIGCONTEXT_FLAGS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #	define CFM_OFF		IA64_SIGCONTEXT_CFM_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #	define FR6_OFF		IA64_SIGCONTEXT_FR6_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #	define BSP_OFF		IA64_SIGCONTEXT_AR_BSP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #	define RNAT_OFF		IA64_SIGCONTEXT_AR_RNAT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #	define UNAT_OFF		IA64_SIGCONTEXT_AR_UNAT_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #	define FPSR_OFF		IA64_SIGCONTEXT_AR_FPSR_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #	define PR_OFF		IA64_SIGCONTEXT_PR_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #	define RP_OFF		IA64_SIGCONTEXT_IP_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #	define SP_OFF		IA64_SIGCONTEXT_R12_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #	define RBS_BASE_OFF	IA64_SIGCONTEXT_RBS_BASE_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #	define LOADRS_OFF	IA64_SIGCONTEXT_LOADRS_OFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #	define base0		r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #	define base1		r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * When we get here, the memory stack looks like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	 *   +===============================+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)        	 *   |				     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)        	 *   //	    struct sigframe          //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)        	 *   |				     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 *   +-------------------------------+ <-- sp+16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	 *   |      16 byte of scratch       |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	 *   |            space              |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 *   +-------------------------------+ <-- sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 * The register stack looks _exactly_ the way it looked at the time the signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	 * occurred.  In other words, we're treading on a potential mine-field: each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * incoming general register may be a NaT value (including sp, in which case the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	 * process ends up dying with a SIGSEGV).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	 * The first thing need to do is a cover to get the registers onto the backing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * store.  Once that is done, we invoke the signal handler which may modify some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * of the machine state.  After returning from the signal handler, we return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * control to the previous context by executing a sigreturn system call.  A signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 * handler may call the rt_sigreturn() function to directly return to a given
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	 * sigcontext.  However, the user-level sigreturn() needs to do much more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	 * calling the rt_sigreturn() system call as it needs to unwind the stack to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	 * restore preserved registers that may have been saved on the signal handler's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	 * call stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIGTRAMP_SAVES										\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	.unwabi 3, 's';		/* mark this as a sigtramp handler (saves scratch regs) */	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	.unwabi @svr4, 's'; /* backwards compatibility with old unwinders (remove in v2.7) */	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	.savesp ar.unat, UNAT_OFF+SIGCONTEXT_OFF;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.savesp ar.fpsr, FPSR_OFF+SIGCONTEXT_OFF;						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	.savesp pr, PR_OFF+SIGCONTEXT_OFF;     							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.savesp rp, RP_OFF+SIGCONTEXT_OFF;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.savesp ar.pfs, CFM_OFF+SIGCONTEXT_OFF;							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.vframesp SP_OFF+SIGCONTEXT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GLOBAL_ENTRY(__kernel_sigtramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	// describe the state that is active when we get here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	SIGTRAMP_SAVES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.label_state 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	adds base0=SIGHANDLER_OFF,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	adds base1=RBS_BASE_OFF+SIGCONTEXT_OFF,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	br.call.sptk.many rp=1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	ld8 r17=[base0],(ARG0_OFF-SIGHANDLER_OFF)	// get pointer to signal handler's plabel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	ld8 r15=[base1]					// get address of new RBS base (or NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	cover				// push args in interrupted frame onto backing store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	cmp.ne p1,p0=r15,r0		// do we need to switch rbs? (note: pr is saved by kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	mov.m r9=ar.bsp			// fetch ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.spillsp.p p1, ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (p1)	br.cond.spnt setup_rbs		// yup -> (clobbers p8, r14-r16, and r18-r20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) back_from_setup_rbs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	alloc r8=ar.pfs,0,0,3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	ld8 out0=[base0],16		// load arg0 (signum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	adds base1=(ARG1_OFF-(RBS_BASE_OFF+SIGCONTEXT_OFF)),base1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	ld8 out1=[base1]		// load arg1 (siginfop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	ld8 r10=[r17],8			// get signal handler entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ld8 out2=[base0]		// load arg2 (sigcontextp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	ld8 gp=[r17]			// get signal handler's global pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.spillsp ar.bsp, BSP_OFF+SIGCONTEXT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	st8 [base0]=r9			// save sc_ar_bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stf.spill [base0]=f6,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	stf.spill [base1]=f7,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	stf.spill [base0]=f8,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	stf.spill [base1]=f9,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mov b6=r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	stf.spill [base0]=f10,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	stf.spill [base1]=f11,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	stf.spill [base0]=f12,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	stf.spill [base1]=f13,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	stf.spill [base0]=f14,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	stf.spill [base1]=f15,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	br.call.sptk.many rp=b6			// call the signal handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .ret0:	adds base0=(BSP_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ld8 r15=[base0]				// fetch sc_ar_bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	mov r14=ar.bsp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	cmp.ne p1,p0=r14,r15			// do we need to restore the rbs?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) (p1)	br.cond.spnt restore_rbs		// yup -> (clobbers r14-r18, f6 & f7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) back_from_restore_rbs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	adds base0=(FR6_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	adds base1=(FR6_OFF+16+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ldf.fill f6=[base0],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	ldf.fill f7=[base1],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	ldf.fill f8=[base0],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	ldf.fill f9=[base1],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ldf.fill f10=[base0],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	ldf.fill f11=[base1],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	ldf.fill f12=[base0],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	ldf.fill f13=[base1],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	ldf.fill f14=[base0],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	ldf.fill f15=[base1],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	mov r15=__NR_rt_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.restore sp				// pop .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	break __BREAK_SYSCALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	SIGTRAMP_SAVES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) setup_rbs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mov ar.rsc=0				// put RSE into enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	.save ar.rnat, r19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mov r19=ar.rnat				// save RNaT before switching backing store area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	adds r14=(RNAT_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mov r18=ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	mov ar.bspstore=r15			// switch over to new register backing store area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	st8 [r14]=r19				// save sc_ar_rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	mov.m r16=ar.bsp			// sc_loadrs <- (new bsp - new bspstore) << 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	adds r14=(LOADRS_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	invala
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	sub r15=r16,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	extr.u r20=r18,3,6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mov ar.rsc=0xf				// set RSE into eager mode, pl 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	cmp.eq p8,p0=63,r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	shl r15=r15,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	st8 [r14]=r15				// save sc_loadrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) (p8)	st8 [r18]=r19		// if bspstore points at RNaT slot, store RNaT there now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.restore sp				// pop .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	br.cond.sptk back_from_setup_rbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	SIGTRAMP_SAVES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	.spillsp ar.rnat, RNAT_OFF+SIGCONTEXT_OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) restore_rbs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	// On input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	//	r14 = bsp1 (bsp at the time of return from signal handler)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	//	r15 = bsp0 (bsp at the time the signal occurred)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	// Here, we need to calculate bspstore0, the value that ar.bspstore needs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	// to be set to, based on bsp0 and the size of the dirty partition on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	// the alternate stack (sc_loadrs >> 16).  This can be done with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	// following algorithm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	//  bspstore0 = rse_skip_regs(bsp0, -rse_num_regs(bsp1 - (loadrs >> 19), bsp1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	// This is what the code below does.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	//
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	alloc r2=ar.pfs,0,0,0,0			// alloc null frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	adds r16=(LOADRS_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	adds r18=(RNAT_OFF+SIGCONTEXT_OFF),sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	ld8 r17=[r16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	ld8 r16=[r18]			// get new rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	extr.u r18=r15,3,6	// r18 <- rse_slot_num(bsp0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mov ar.rsc=r17			// put RSE into enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	shr.u r17=r17,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	sub r14=r14,r17		// r14 (bspstore1) <- bsp1 - (sc_loadrs >> 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	shr.u r17=r17,3		// r17 <- (sc_loadrs >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	loadrs			// restore dirty partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	extr.u r14=r14,3,6	// r14 <- rse_slot_num(bspstore1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	add r14=r14,r17		// r14 <- rse_slot_num(bspstore1) + (sc_loadrs >> 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	shr.u r14=r14,6		// r14 <- (rse_slot_num(bspstore1) + (sc_loadrs >> 19))/0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	sub r14=r14,r17		// r14 <- -rse_num_regs(bspstore1, bsp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	movl r17=0x8208208208208209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	add r18=r18,r14		// r18 (delta) <- rse_slot_num(bsp0) - rse_num_regs(bspstore1,bsp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	setf.sig f7=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	cmp.lt p7,p0=r14,r0	// p7 <- (r14 < 0)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) (p7)	adds r18=-62,r18	// delta -= 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	setf.sig f6=r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	xmpy.h f6=f6,f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	getf.sig r17=f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	add r17=r17,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	shr r18=r18,63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	shr r17=r17,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	sub r17=r17,r18		// r17 = delta/63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	add r17=r14,r17		// r17 <- delta/63 - rse_num_regs(bspstore1, bsp1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	shladd r15=r17,3,r15	// r15 <- bsp0 + 8*(delta/63 - rse_num_regs(bspstore1, bsp1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	mov ar.bspstore=r15			// switch back to old register backing store area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mov ar.rnat=r16				// restore RNaT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	mov ar.rsc=0xf				// (will be restored later on from sc_ar_rsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	// invala not necessary as that will happen when returning to user-mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	br.cond.sptk back_from_restore_rbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) END(__kernel_sigtramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)  * On entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)  *	r11 = saved ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)  *	r15 = system call #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)  *	b0  = saved return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)  *	b6  = return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)  * On exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)  *	r11 = saved ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)  *	r15 = system call #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)  *	b0  = saved return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)  *	all other "scratch" registers:	undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)  *	all "preserved" registers:	same as on entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GLOBAL_ENTRY(__kernel_syscall_via_epc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	.prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	.altrp b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	.body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * Note: the kernel cannot assume that the first two instructions in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 * bundle get executed.  The remaining code must be safe even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 * they do not get executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	adds r17=-1024,r15			// A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	mov r10=0				// A    default to successful syscall execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	epc					// B	causes split-issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	RSM_PSR_BE_I(r20, r22)			// M2 (5 cyc to srlz.d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	LOAD_FSYSCALL_TABLE(r14)		// X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	mov r16=IA64_KR(CURRENT)		// M2 (12 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	shladd r18=r17,3,r14			// A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	mov r19=NR_syscalls-1			// A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	lfetch [r18]				// M0|1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	MOV_FROM_PSR(p0, r29, r8)		// M2 (12 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	// If r17 is a NaT, p6 will be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	cmp.geu p6,p7=r19,r17			// A    (sysnr > 0 && sysnr < 1024+NR_syscalls)?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	mov r21=ar.fpsr				// M2 (12 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	tnat.nz p10,p9=r15			// I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	mov.i r26=ar.pfs			// I0 (would stall anyhow due to srlz.d...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	srlz.d					// M0 (forces split-issue) ensure PSR.BE==0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (p6)	ld8 r18=[r18]				// M0|1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	nop.m 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) (p6)	tbit.z.unc p8,p0=r18,0			// I0 (dual-issues with "mov b7=r18"!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	SSM_PSR_I(p8, p14, r25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (p6)	mov b7=r18				// I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) (p8)	br.dptk.many b7				// B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	mov r27=ar.rsc				// M2 (12 cyc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)  * brl.cond doesn't work as intended because the linker would convert this branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * into a branch to a PLT.  Perhaps there will be a way to avoid this with some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * future version of the linker.  In the meantime, we just use an indirect branch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (p6)	add r14=-8,r14				// r14 <- addr of fsys_bubble_down entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) (p6)	ld8 r14=[r14]				// r14 <- fsys_bubble_down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) (p6)	mov b7=r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) (p6)	br.sptk.many b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	BRL_COND_FSYS_BUBBLE_DOWN(p6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	SSM_PSR_I(p0, p14, r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mov r10=-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (p10)	mov r8=EINVAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) (p9)	mov r8=ENOSYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	FSYS_RETURN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) END(__kernel_syscall_via_epc)