^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Preserved registers that are shared between code in ivt.S and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * entry.S. Be careful not to step on these!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PRED_LEAVE_SYSCALL 1 /* TRUE iff leave from syscall */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define PRED_KERNEL_STACK 2 /* returning to kernel-stacks? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define PRED_USER_STACK 3 /* returning to user-stacks? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PRED_SYSCALL 4 /* inside a system call? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PRED_NON_SYSCALL 5 /* complement of PRED_SYSCALL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifdef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) # define PASTE2(x,y) x##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # define PASTE(x,y) PASTE2(x,y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) # define pLvSys PASTE(p,PRED_LEAVE_SYSCALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) # define pKStk PASTE(p,PRED_KERNEL_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) # define pUStk PASTE(p,PRED_USER_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define pSys PASTE(p,PRED_SYSCALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define pNonSys PASTE(p,PRED_NON_SYSCALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PT(f) (IA64_PT_REGS_##f##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SW(f) (IA64_SWITCH_STACK_##f##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SOS(f) (IA64_SAL_OS_STATE_##f##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PT_REGS_SAVES(off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .unwabi 3, 'i'; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .fframe IA64_PT_REGS_SIZE+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .spillsp rp, PT(CR_IIP)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .spillsp ar.pfs, PT(CR_IFS)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .spillsp ar.unat, PT(AR_UNAT)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .spillsp ar.fpsr, PT(AR_FPSR)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .spillsp pr, PT(PR)+16+(off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PT_REGS_UNWIND_INFO(off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .prologue; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PT_REGS_SAVES(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SWITCH_STACK_SAVES(off) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .savesp ar.unat,SW(CALLER_UNAT)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .savesp ar.fpsr,SW(AR_FPSR)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .spillsp @priunat,SW(AR_UNAT)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .spillsp ar.rnat,SW(AR_RNAT)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .spillsp pr,SW(PR)+16+(off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DO_SAVE_SWITCH_STACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) movl r28=1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .fframe IA64_SWITCH_STACK_SIZE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) adds sp=-IA64_SWITCH_STACK_SIZE,sp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mov.ret.sptk b7=r28,1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) SWITCH_STACK_SAVES(0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) br.cond.sptk.many save_switch_stack; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DO_LOAD_SWITCH_STACK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) movl r28=1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ;; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) invala; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) mov.ret.sptk b7=r28,1f; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) br.cond.sptk.many load_switch_stack; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 1: .restore sp; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) adds sp=IA64_SWITCH_STACK_SIZE,sp
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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