^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/ia64/kernel/entry.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Kernel entry points.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 1999, 2002-2003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Asit Mallick <Asit.K.Mallick@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Don Dugger <Don.Dugger@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Suresh Siddha <suresh.b.siddha@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Fenghua Yu <fenghua.yu@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1999 VA Linux Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * ia64_switch_to now places correct virtual mapping in in TR2 for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * kernel stack. This allows us to handle interrupts without changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * to physical mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Jonathan Nicklin <nicklin@missioncriticallinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Patrick O'Rourke <orourke@missioncriticallinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 11/07/2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Copyright (c) 2008 Isaku Yamahata <yamahata at valinux co jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * VA Linux Systems Japan K.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * pv_ops.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Global (preserved) predicate usage on syscall entry/exit path:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * pKStk: See entry.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * pUStk: See entry.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * pSys: See entry.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * pNonSys: !pSys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/asmmacro.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <asm/kregs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <asm/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <asm/ftrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <asm/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include "minstate.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * execve() is special because in case of success, we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * setup a null register window frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ENTRY(ia64_execve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Allocate 8 input registers since ptrace() may clobber them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) alloc loc1=ar.pfs,8,2,3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mov out0=in0 // filename
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ;; // stop bit between alloc and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mov out1=in1 // argv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mov out2=in2 // envp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) br.call.sptk.many rp=sys_execve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .ret0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) cmp4.ge p6,p7=r8,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mov ar.pfs=loc1 // restore ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) sxt4 r8=r8 // return 64-bit result
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) stf.spill [sp]=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) (p6) mov ar.pfs=r0 // clear ar.pfs on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) (p7) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * In theory, we'd have to zap this state only to prevent leaking of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * security sensitive state (e.g., if current->mm->dumpable is zero). However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * this executes in less than 20 cycles even on Itanium, so it's not worth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * optimizing for...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) mov ar.unat=0; mov ar.lc=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mov r4=0; mov f2=f0; mov b1=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mov r5=0; mov f3=f0; mov b2=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) mov r6=0; mov f4=f0; mov b3=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mov r7=0; mov f5=f0; mov b4=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ldf.fill f12=[sp]; mov f13=f0; mov b5=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ldf.fill f14=[sp]; ldf.fill f15=[sp]; mov f16=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ldf.fill f17=[sp]; ldf.fill f18=[sp]; mov f19=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ldf.fill f20=[sp]; ldf.fill f21=[sp]; mov f22=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ldf.fill f23=[sp]; ldf.fill f24=[sp]; mov f25=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ldf.fill f26=[sp]; ldf.fill f27=[sp]; mov f28=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ldf.fill f29=[sp]; ldf.fill f30=[sp]; mov f31=f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) END(ia64_execve)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * u64 tls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) GLOBAL_ENTRY(sys_clone2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Allocate 8 input registers since ptrace() may clobber them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) alloc r16=ar.pfs,8,2,6,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DO_SAVE_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mov loc1=r16 // save ar.pfs across ia64_clone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) mov out0=in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) mov out1=in1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) mov out2=in2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) mov out3=in3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) mov out4=in4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) mov out5=in5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) br.call.sptk.many rp=ia64_clone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ret1: .restore sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) END(sys_clone2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Deprecated. Use sys_clone2() instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GLOBAL_ENTRY(sys_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Allocate 8 input registers since ptrace() may clobber them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) alloc r16=ar.pfs,8,2,6,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DO_SAVE_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) mov loc1=r16 // save ar.pfs across ia64_clone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) mov out0=in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mov out1=in1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) mov out2=16 // stacksize (compensates for 16-byte scratch area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) mov out3=in3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mov out4=in4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mov out5=in5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) br.call.sptk.many rp=ia64_clone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ret2: .restore sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) adds sp=IA64_SWITCH_STACK_SIZE,sp // pop the switch stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) END(sys_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * prev_task <- ia64_switch_to(struct task_struct *next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * With Ingo's new scheduler, interrupts are disabled when this routine gets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * called. The code starting at .map relies on this. The rest of the code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * doesn't care about the interrupt masking status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) GLOBAL_ENTRY(ia64_switch_to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) alloc r16=ar.pfs,1,0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) DO_SAVE_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) movl r25=init_task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) mov r27=IA64_KR(CURRENT_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dep r20=0,in0,61,3 // physical address of "next"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) st8 [r22]=sp // save kernel stack pointer of old task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) shr.u r26=r20,IA64_GRANULE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) cmp.eq p7,p6=r25,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * If we've already mapped this task's page, we can skip doing it again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) (p6) cmp.eq p7,p6=r26,r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) (p6) br.cond.dpnt .map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ld8 sp=[r21] // load kernel stack pointer of new task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MOV_TO_KR(CURRENT, in0, r8, r9) // update "current" application register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mov r8=r13 // return pointer to previously running task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mov r13=in0 // set "current" pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DO_LOAD_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) sync.i // ensure "fc"s done by this CPU are visible on other CPUs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) br.ret.sptk.many rp // boogie on out in new context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) RSM_PSR_IC(r25) // interrupts (psr.i) are already disabled here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) movl r25=PAGE_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) srlz.d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) or r23=r25,r20 // construct PA | page properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) mov r25=IA64_GRANULE_SHIFT<<2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MOV_TO_ITIR(p0, r25, r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MOV_TO_IFA(in0, r8) // VA of next task...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mov r25=IA64_TR_CURRENT_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MOV_TO_KR(CURRENT_STACK, r26, r8, r9) // remember last page we mapped...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) itr.d dtr[r25]=r23 // wire in new mapping...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SSM_PSR_IC_AND_SRLZ_D(r8, r9) // reenable the psr.ic bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) br.cond.sptk .done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) END(ia64_switch_to)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * Note that interrupts are enabled during save_switch_stack and load_switch_stack. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * means that we may get an interrupt with "sp" pointing to the new kernel stack while
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * ar.bspstore is still pointing to the old kernel backing store area. Since ar.rsc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * problem. Also, we don't need to specify unwind information for preserved registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * that are not modified in save_switch_stack as the right unwind information is already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * specified at the call-site of save_switch_stack.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * save_switch_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * - r16 holds ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * - b7 holds address to return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * - rp (b0) holds return address to save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GLOBAL_ENTRY(save_switch_stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .altrp b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) flushrs // flush dirty regs to backing store (must be first in insn group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .save @priunat,r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mov r17=ar.unat // preserve caller's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) adds r2=16+128,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) adds r3=16+64,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) adds r14=SW(R4)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) st8.spill [r14]=r4,16 // spill r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) lfetch.fault.excl.nt1 [r3],128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) lfetch.fault.excl.nt1 [r2],128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) lfetch.fault.excl.nt1 [r3],128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) lfetch.fault.excl [r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) lfetch.fault.excl [r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) adds r15=SW(R5)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) add r2=16+3*128,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) add r3=16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) add r14=SW(R4)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) st8.spill [r14]=r4,SW(R6)-SW(R4) // spill r4 and prefetch offset 0x1c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) lfetch.fault.excl.nt1 [r3],128 // prefetch offset 0x090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) lfetch.fault.excl.nt1 [r2],128 // prefetch offset 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) lfetch.fault.excl.nt1 [r3] // prefetch offset 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) lfetch.fault.excl.nt1 [r2] // prefetch offset 0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) adds r15=SW(R5)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) st8.spill [r15]=r5,SW(R7)-SW(R5) // spill r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mov.m ar.rsc=0 // put RSE in mode: enforced lazy, little endian, pl 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) add r2=SW(F2)+16,sp // r2 = &sw->f2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) st8.spill [r14]=r6,SW(B0)-SW(R6) // spill r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mov.m r18=ar.fpsr // preserve fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) add r3=SW(F3)+16,sp // r3 = &sw->f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) stf.spill [r2]=f2,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mov.m r19=ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mov r21=b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) stf.spill [r3]=f3,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) st8.spill [r15]=r7,SW(B2)-SW(R7) // spill r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mov r22=b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) // since we're done with the spills, read and save ar.unat:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mov.m r29=ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mov.m r20=ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mov r23=b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) stf.spill [r2]=f4,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) stf.spill [r3]=f5,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mov r24=b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) st8 [r14]=r21,SW(B1)-SW(B0) // save b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) st8 [r15]=r23,SW(B3)-SW(B2) // save b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mov r25=b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mov r26=b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) st8 [r14]=r22,SW(B4)-SW(B1) // save b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) st8 [r15]=r24,SW(AR_PFS)-SW(B3) // save b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mov r21=ar.lc // I-unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) stf.spill [r2]=f12,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) stf.spill [r3]=f13,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) st8 [r14]=r25,SW(B5)-SW(B4) // save b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS) // save ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) stf.spill [r2]=f14,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) stf.spill [r3]=f15,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) st8 [r14]=r26 // save b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) st8 [r15]=r21 // save ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) stf.spill [r2]=f16,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) stf.spill [r3]=f17,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) stf.spill [r2]=f18,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) stf.spill [r3]=f19,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) stf.spill [r2]=f20,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) stf.spill [r3]=f21,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) stf.spill [r2]=f22,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) stf.spill [r3]=f23,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) stf.spill [r2]=f24,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) stf.spill [r3]=f25,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) stf.spill [r2]=f26,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) stf.spill [r3]=f27,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) stf.spill [r2]=f28,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) stf.spill [r3]=f29,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) stf.spill [r3]=f31,SW(PR)-SW(F31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) add r14=SW(CALLER_UNAT)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT) // save ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mov r21=pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) st8 [r3]=r21 // save predicate registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) st8 [r2]=r20 // save ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) st8 [r14]=r18 // save fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) mov ar.rsc=3 // put RSE back into eager mode, pl 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) br.cond.sptk.many b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) END(save_switch_stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * load_switch_stack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * - "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * - b7 holds address to return to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * - must not touch r8-r11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GLOBAL_ENTRY(load_switch_stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .altrp b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) lfetch.fault.nt1 [sp]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) adds r2=SW(AR_BSPSTORE)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) adds r3=SW(AR_UNAT)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) mov ar.rsc=0 // put RSE into enforced lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) adds r14=SW(CALLER_UNAT)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) adds r15=SW(AR_FPSR)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE)) // bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) ld8 r29=[r3],(SW(B1)-SW(AR_UNAT)) // unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ld8 r21=[r2],16 // restore b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ld8 r22=[r3],16 // restore b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ld8 r23=[r2],16 // restore b2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ld8 r24=[r3],16 // restore b3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ld8 r25=[r2],16 // restore b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ld8 r26=[r3],16 // restore b5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ld8 r16=[r2],(SW(PR)-SW(AR_PFS)) // ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC)) // ar.lc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ld8 r28=[r2] // restore pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ld8 r30=[r3] // restore rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ld8 r18=[r14],16 // restore caller's unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ld8 r19=[r15],24 // restore fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ldf.fill f2=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) ldf.fill f3=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ldf.fill f4=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ldf.fill f5=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ldf.fill f12=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ldf.fill f13=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ldf.fill f14=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ldf.fill f15=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ldf.fill f16=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ldf.fill f17=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ldf.fill f18=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ldf.fill f19=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mov b0=r21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ldf.fill f20=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ldf.fill f21=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) mov b1=r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ldf.fill f22=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ldf.fill f23=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mov b2=r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mov ar.bspstore=r27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mov ar.unat=r29 // establish unat holding the NaT bits for r4-r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) mov b3=r24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ldf.fill f24=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ldf.fill f25=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) mov b4=r25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ldf.fill f26=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ldf.fill f27=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) mov b5=r26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ldf.fill f28=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ldf.fill f29=[r15],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) mov ar.pfs=r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ldf.fill f30=[r14],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ldf.fill f31=[r15],24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mov ar.lc=r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ld8.fill r4=[r14],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ld8.fill r5=[r15],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mov pr=r28,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ld8.fill r6=[r14],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ld8.fill r7=[r15],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mov ar.unat=r18 // restore caller's unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mov ar.rnat=r30 // must restore after bspstore but before rsc!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mov ar.fpsr=r19 // restore fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mov ar.rsc=3 // put RSE back into eager mode, pl 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) br.cond.sptk.many b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) END(load_switch_stack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * Invoke a system call, but do some tracing before and after the call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * We MUST preserve the current register frame throughout this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * because some system calls (such as ia64_execve) directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * manipulate ar.pfs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) GLOBAL_ENTRY(ia64_trace_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * We need to preserve the scratch registers f6-f11 in case the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * call is sigreturn.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) adds r16=PT(F6)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) adds r17=PT(F7)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) stf.spill [r16]=f6,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) stf.spill [r17]=f7,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) stf.spill [r16]=f8,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) stf.spill [r17]=f9,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) stf.spill [r16]=f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) stf.spill [r17]=f11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) cmp.lt p6,p0=r8,r0 // check tracehook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) mov r10=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) (p6) br.cond.sptk strace_error // syscall failed ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) adds r16=PT(F6)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) adds r17=PT(F7)+16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ldf.fill f6=[r16],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ldf.fill f7=[r17],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ldf.fill f8=[r16],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) ldf.fill f9=[r17],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ldf.fill f10=[r16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ldf.fill f11=[r17]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) // the syscall number may have changed, so re-load it and re-calculate the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) // syscall entry-point:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) adds r15=PT(R15)+16,sp // r15 = &pt_regs.r15 (syscall #)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ld8 r15=[r15]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mov r3=NR_syscalls - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) adds r15=-1024,r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) movl r16=sys_call_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) cmp.leu p6,p7=r15,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) (p6) ld8 r20=[r20] // load address of syscall entry point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) (p7) movl r20=sys_ni_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mov b6=r20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) br.call.sptk.many rp=b6 // do the syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .strace_check_retval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cmp.lt p6,p0=r8,r0 // syscall failed?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) adds r3=PT(R10)+16,sp // r3 = &pt_regs.r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mov r10=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) (p6) br.cond.sptk strace_error // syscall failed ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ;; // avoid RAW on r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .strace_save_retval:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .mem.offset 0,0; st8.spill [r2]=r8 // store return value in slot for r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .mem.offset 8,0; st8.spill [r3]=r10 // clear error indication in slot for r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .ret3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (pUStk) rsm psr.i // disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) br.cond.sptk ia64_work_pending_syscall_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) strace_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ld8 r3=[r2] // load pt_regs.r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) sub r9=0,r8 // negate return value to get errno value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) cmp.ne p6,p0=r3,r0 // is pt_regs.r8!=0?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) adds r3=16,r2 // r3=&pt_regs.r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) (p6) mov r10=-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) (p6) mov r8=r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) br.cond.sptk .strace_save_retval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) END(ia64_trace_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * When traced and returning from sigreturn, we invoke syscall_trace but then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GLOBAL_ENTRY(ia64_strace_leave_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * Some versions of gas generate bad unwind info if the first instruction of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * procedure doesn't go into the first slot of a bundle. This is a workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) nop.m 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ret4: br.cond.sptk ia64_leave_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) END(ia64_strace_leave_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ENTRY(call_payload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* call the kernel_thread payload; fn is in r4, arg - in r5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) alloc loc1=ar.pfs,0,3,1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) mov loc2=gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mov out0=r5 // arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ld8 r14 = [r4], 8 // fn.address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mov b6 = r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ld8 gp = [r4] // fn.gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) br.call.sptk.many rp=b6 // fn(arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ret12: mov gp=loc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* ... and if it has returned, we are going to userland */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) cmp.ne pKStk,pUStk=r0,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) END(call_payload)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GLOBAL_ENTRY(ia64_ret_from_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) { /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * Some versions of gas generate bad unwind info if the first instruction of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * procedure doesn't go into the first slot of a bundle. This is a workaround.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) nop.m 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * We need to call schedule_tail() to complete the scheduling process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * Called by ia64_switch_to() after ia64_clone()->copy_thread(). r8 contains the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * address of the previously executing task.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) br.call.sptk.many rp=ia64_invoke_schedule_tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .ret8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) (pKStk) br.call.sptk.many rp=call_payload
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) ld4 r2=[r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mov r8=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) and r2=_TIF_SYSCALL_TRACEAUDIT,r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) cmp.ne p6,p0=r2,r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) (p6) br.cond.spnt .strace_check_retval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ;; // added stop bits to prevent r8 dependency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) END(ia64_ret_from_clone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) // fall through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GLOBAL_ENTRY(ia64_ret_from_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cmp.ge p6,p7=r8,r0 // syscall executed successfully?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) adds r2=PT(R8)+16,sp // r2 = &pt_regs.r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mov r10=r0 // clear error indication in r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (p7) br.cond.spnt handle_syscall_error // handle potential syscall failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) END(ia64_ret_from_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) // fall through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * need to switch to bank 0 and doesn't restore the scratch registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * To avoid leaking kernel bits, the scratch registers are set to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * the following known-to-be-safe values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * r1: restored (global pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * r2: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * r3: 1 (when returning to user-level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * r8-r11: restored (syscall return value(s))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * r12: restored (user-level stack pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * r13: restored (user-level thread pointer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * r14: set to __kernel_syscall_via_epc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * r15: restored (syscall #)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * r16-r17: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * r18: user-level b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * r19: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * r20: user-level ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * r21: user-level b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * r22: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * r23: user-level ar.bspstore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * r24: user-level ar.rnat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * r25: user-level ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * r26: user-level ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * r27: user-level ar.rsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) * r28: user-level ip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * r29: user-level psr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * r30: user-level cfm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * r31: user-level pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * f6-f11: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * pr: restored (user-level pr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * b0: restored (user-level rp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * b6: restored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * b7: set to __kernel_syscall_via_epc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * ar.unat: restored (user-level ar.unat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * ar.pfs: restored (user-level ar.pfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * ar.rsc: restored (user-level ar.rsc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * ar.rnat: restored (user-level ar.rnat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * ar.bspstore: restored (user-level ar.bspstore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * ar.fpsr: restored (user-level ar.fpsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * ar.ccv: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * ar.csd: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * ar.ssd: cleared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) GLOBAL_ENTRY(ia64_leave_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * work.need_resched etc. mustn't get changed by this CPU before it returns to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * user- or fsys-mode, hence we disable interrupts early on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * p6 controls whether current_thread_info()->flags needs to be check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * extra work. We always check for extra work when returning to user-level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * With CONFIG_PREEMPTION, we also check for extra work when the preempt_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * is 0. After extra work processing has been completed, execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * resumes at ia64_work_processed_syscall with p6 set to 1 if the extra-work-check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * needs to be redone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #ifdef CONFIG_PREEMPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RSM_PSR_I(p0, r2, r18) // disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .pred.rel.mutex pUStk,pKStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (pKStk) ld4 r21=[r20] // r21 <- preempt_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) (pUStk) mov r21=0 // r21 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #else /* !CONFIG_PREEMPTION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RSM_PSR_I(pUStk, r2, r18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) cmp.eq pLvSys,p0=r0,r0 // pLvSys=1: leave from syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .global ia64_work_processed_syscall;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ia64_work_processed_syscall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) adds r2=PT(LOADRS)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MOV_FROM_ITC(pUStk, p9, r22, r19) // fetch time at leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (p6) ld4 r31=[r18] // load current_thread_info()->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) adds r3=PT(AR_BSPSTORE)+16,r12 // deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) adds r2=PT(LOADRS)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) adds r3=PT(AR_BSPSTORE)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) (p6) ld4 r31=[r18] // load current_thread_info()->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ld8 r19=[r2],PT(B6)-PT(LOADRS) // load ar.rsc value for "loadrs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mov r16=ar.bsp // M2 get existing backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ld8 r18=[r2],PT(R9)-PT(B6) // load b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) (p6) and r15=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE) // load ar.bspstore (may be garbage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) (p6) cmp4.ne.unc p6,p0=r15, r0 // any special work pending?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (p6) br.cond.spnt .work_pending_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) // start restoring the state saved on the kernel stack (struct pt_regs):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ld8 r11=[r3],PT(CR_IIP)-PT(R11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) (pNonSys) break 0 // bug check: we shouldn't be here if pNonSys is TRUE!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) invala // M0|1 invalidate ALAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) RSM_PSR_I_IC(r28, r29, r30) // M2 turn off interrupts and interruption collection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) cmp.eq p9,p0=r0,r0 // A set p9 to indicate that we should restore cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ld8 r29=[r2],16 // M0|1 load cr.ipsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ld8 r28=[r3],16 // M0|1 load cr.iip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (pUStk) add r14=TI_AC_LEAVE+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ld8 r30=[r2],16 // M0|1 load cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ld8 r25=[r3],16 // M0|1 load ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) (pUStk) add r15=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) mov r22=r0 // A clear r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ld8 r30=[r2],16 // M0|1 load cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ld8 r25=[r3],16 // M0|1 load ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) (pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ld8 r26=[r2],PT(B0)-PT(AR_PFS) // M0|1 load ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) MOV_FROM_PSR(pKStk, r22, r21) // M2 read PSR now that interrupts are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) nop 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // M0|1 load b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ld8 r27=[r3],PT(PR)-PT(AR_RSC) // M0|1 load ar.rsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) mov f6=f0 // F clear f6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT) // M0|1 load ar.rnat (may be garbage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ld8 r31=[r3],PT(R1)-PT(PR) // M0|1 load predicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mov f7=f0 // F clear f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ld8 r20=[r2],PT(R12)-PT(AR_FPSR) // M0|1 load ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ld8.fill r1=[r3],16 // M0|1 load r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (pUStk) mov r17=1 // A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) (pUStk) st1 [r15]=r17 // M2|3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) (pUStk) st1 [r14]=r17 // M2|3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ld8.fill r13=[r3],16 // M0|1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mov f8=f0 // F clear f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ld8.fill r12=[r2] // M0|1 restore r12 (sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ld8.fill r15=[r3] // M0|1 restore r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) mov b6=r18 // I0 restore b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) LOAD_PHYS_STACK_REG_SIZE(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mov f9=f0 // F clear f9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) (pKStk) br.cond.dpnt.many skip_rbs_switch // B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) srlz.d // M0 ensure interruption collection is off (for cover)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) shr.u r18=r19,16 // I0|1 get byte size of existing "dirty" partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) COVER // B add current frame into dirty partition & set cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) mov r19=ar.bsp // M2 get new backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) st8 [r14]=r22 // M save time at leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mov f10=f0 // F clear f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) mov r22=r0 // A clear r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) movl r14=__kernel_syscall_via_epc // X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mov r19=ar.bsp // M2 get new backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mov f10=f0 // F clear f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) nop.m 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) movl r14=__kernel_syscall_via_epc // X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) mov.m ar.csd=r0 // M2 clear ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) mov.m ar.ccv=r0 // M2 clear ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mov b7=r14 // I0 clear b7 (hint with __kernel_syscall_via_epc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mov.m ar.ssd=r0 // M2 clear ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mov f11=f0 // F clear f11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) br.cond.sptk.many rbs_switch // B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) END(ia64_leave_syscall)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GLOBAL_ENTRY(ia64_leave_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) * work.need_resched etc. mustn't get changed by this CPU before it returns to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * user- or fsys-mode, hence we disable interrupts early on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * p6 controls whether current_thread_info()->flags needs to be check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * extra work. We always check for extra work when returning to user-level.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * With CONFIG_PREEMPTION, we also check for extra work when the preempt_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * is 0. After extra work processing has been completed, execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * needs to be redone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #ifdef CONFIG_PREEMPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) RSM_PSR_I(p0, r17, r31) // disable interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) (pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .pred.rel.mutex pUStk,pKStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) (pKStk) ld4 r21=[r20] // r21 <- preempt_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (pUStk) mov r21=0 // r21 <- 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) cmp.eq p6,p0=r21,r0 // p6 <- pUStk || (preempt_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) RSM_PSR_I(pUStk, r17, r31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) cmp.eq p0,pLvSys=r0,r0 // pLvSys=0: leave from kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (pUStk) cmp.eq.unc p6,p0=r0,r0 // p6 <- pUStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .work_processed_kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) (p6) ld4 r31=[r17] // load current_thread_info()->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) adds r21=PT(PR)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) lfetch [r21],PT(CR_IPSR)-PT(PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) adds r2=PT(B6)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) adds r3=PT(R16)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) lfetch [r21]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ld8 r28=[r2],8 // load b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) adds r29=PT(R24)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ld8.fill r16=[r3],PT(AR_CSD)-PT(R16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) adds r30=PT(AR_CCV)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) (p6) and r19=TIF_WORK_MASK,r31 // any work other than TIF_SYSCALL_TRACE?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ld8.fill r24=[r29]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ld8 r15=[r30] // load ar.ccv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) (p6) cmp4.ne.unc p6,p0=r19, r0 // any special work pending?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ld8 r29=[r2],16 // load b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ld8 r30=[r3],16 // load ar.csd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) (p6) br.cond.spnt .work_pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ld8 r31=[r2],16 // load ar.ssd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ld8.fill r8=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ld8.fill r9=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ld8.fill r10=[r3],PT(R17)-PT(R10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ld8.fill r11=[r2],PT(R18)-PT(R11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ld8.fill r17=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ld8.fill r18=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ld8.fill r19=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ld8.fill r20=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ld8.fill r21=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mov ar.csd=r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) mov ar.ssd=r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RSM_PSR_I_IC(r23, r22, r25) // initiate turning off of interrupt and interruption collection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) invala // invalidate ALAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ld8.fill r22=[r2],24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ld8.fill r23=[r3],24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mov b6=r28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ld8.fill r25=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ld8.fill r26=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mov b7=r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ld8.fill r27=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ld8.fill r28=[r3],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ld8.fill r29=[r2],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ld8.fill r30=[r3],24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ld8.fill r31=[r2],PT(F9)-PT(R31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) adds r3=PT(F10)-PT(F6),r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ldf.fill f9=[r2],PT(F6)-PT(F9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ldf.fill f10=[r3],PT(F8)-PT(F10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ldf.fill f6=[r2],PT(F7)-PT(F6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ldf.fill f7=[r2],PT(F11)-PT(F7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ldf.fill f8=[r3],32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) srlz.d // ensure that inter. collection is off (VHPT is don't care, since text is pinned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) mov ar.ccv=r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ldf.fill f11=[r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) BSW_0(r2, r3, r15) // switch back to bank 0 (no stop bit required beforehand...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) (pUStk) mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) adds r16=PT(CR_IPSR)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) adds r17=PT(CR_IIP)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .pred.rel.mutex pUStk,pKStk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MOV_FROM_ITC(pUStk, p9, r22, r29) // M fetch time at leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) MOV_FROM_PSR(pKStk, r22, r29) // M2 read PSR now that interrupts are disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) nop.i 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ld8 r29=[r16],16 // load cr.ipsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ld8 r28=[r17],16 // load cr.iip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ld8 r30=[r16],16 // load cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ld8 r25=[r17],16 // load ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ld8 r26=[r16],16 // load ar.pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ld8 r27=[r17],16 // load ar.rsc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) cmp.eq p9,p0=r0,r0 // set p9 to indicate that we should restore cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ld8 r24=[r16],16 // load ar.rnat (may be garbage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ld8 r23=[r17],16 // load ar.bspstore (may be garbage)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ld8 r31=[r16],16 // load predicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ld8 r21=[r17],16 // load b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ld8 r19=[r16],16 // load ar.rsc value for "loadrs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ld8.fill r1=[r17],16 // load r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ld8.fill r12=[r16],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ld8.fill r13=[r17],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) (pUStk) adds r3=TI_AC_LEAVE+IA64_TASK_SIZE,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ld8 r20=[r16],16 // ar.fpsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ld8.fill r15=[r17],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) (pUStk) adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18 // deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ld8.fill r14=[r16],16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ld8.fill r2=[r17]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) (pUStk) mov r17=1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) // mmi_ : ld8 st1 shr;; mmi_ : st8 st1 shr;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) // mib : mov add br -> mib : ld8 add br
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) // bbb_ : br nop cover;; mbb_ : mov br cover;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) // no one require bsp in r16 if (pKStk) branch is selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) (pUStk) st8 [r3]=r22 // save time at leave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) shr.u r18=r19,16 // get byte size of existing "dirty" partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ld8.fill r3=[r16] // deferred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) LOAD_PHYS_STACK_REG_SIZE(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) (pKStk) br.cond.dpnt skip_rbs_switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mov r16=ar.bsp // get existing backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ld8.fill r3=[r16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) (pUStk) st1 [r18]=r17 // restore current->thread.on_ustack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) shr.u r18=r19,16 // get byte size of existing "dirty" partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mov r16=ar.bsp // get existing backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) LOAD_PHYS_STACK_REG_SIZE(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) (pKStk) br.cond.dpnt skip_rbs_switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * Restore user backing store.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * NOTE: alloc, loadrs, and cover can't be predicated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) (pNonSys) br.cond.dpnt dont_preserve_current_frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) COVER // add current frame into dirty partition and set cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mov r19=ar.bsp // get new backing store pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) rbs_switch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) sub r16=r16,r18 // krbs = old bsp - size of dirty partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) cmp.ne p9,p0=r0,r0 // clear p9 to skip restore of cr.ifs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) sub r19=r19,r16 // calculate total byte size of dirty partition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) add r18=64,r18 // don't force in0-in7 into memory...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) shl r19=r19,16 // shift size of dirty partition into loadrs position
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dont_preserve_current_frame:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) * To prevent leaking bits between the kernel and user-space,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * we must clear the stacked registers in the "invalid" partition here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * 5 registers/cycle on McKinley).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) # define pRecurse p6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) # define pReturn p7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) # define Nregs 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) # define Nregs 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) alloc loc0=ar.pfs,2,Nregs-2,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) shr.u loc1=r18,9 // RNaTslots <= floor(dirtySize / (64*8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sub r17=r17,r18 // r17 = (physStackedSize + 8) - dirtySize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mov ar.rsc=r19 // load ar.rsc to be used for "loadrs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) shladd in0=loc1,3,r17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) mov in1=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) TEXT_ALIGN(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) rse_clear_invalid:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #ifdef CONFIG_ITANIUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) // cycle 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) { .mii
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) alloc loc0=ar.pfs,2,Nregs-2,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) add out0=-Nregs*8,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }{ .mfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) add out1=1,in1 // increment recursion count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) nop.f 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) nop.b 0 // can't do br.call here because of alloc (WAW on CFM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }{ .mfi // cycle 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) mov loc1=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) nop.f 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mov loc2=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }{ .mib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mov loc3=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mov loc4=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) (pRecurse) br.call.sptk.many b0=rse_clear_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }{ .mfi // cycle 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mov loc5=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) nop.f 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }{ .mib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mov loc6=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) mov loc7=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) (pReturn) br.ret.sptk.many b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) #else /* !CONFIG_ITANIUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) alloc loc0=ar.pfs,2,Nregs-2,2,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) cmp.lt pRecurse,p0=Nregs*8,in0 // if more than Nregs regs left to clear, (re)curse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) add out0=-Nregs*8,in0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) add out1=1,in1 // increment recursion count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mov loc1=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mov loc2=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) mov loc3=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) mov loc4=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) mov loc5=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) mov loc6=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) mov loc7=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) (pRecurse) br.call.dptk.few b0=rse_clear_invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mov loc8=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mov loc9=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) cmp.ne pReturn,p0=r0,in1 // if recursion count != 0, we need to do a br.ret
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mov loc10=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mov loc11=0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) (pReturn) br.ret.dptk.many b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #endif /* !CONFIG_ITANIUM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) # undef pRecurse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) # undef pReturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) alloc r17=ar.pfs,0,0,0,0 // drop current register frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) loadrs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) skip_rbs_switch:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mov ar.unat=r25 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) (pKStk) extr.u r22=r22,21,1 // I0 extract current value of psr.pp from r22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) (pLvSys)mov r19=r0 // A clear r19 for leave_syscall, no-op otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) (pUStk) mov ar.bspstore=r23 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (pKStk) dep r29=r22,r29,21,1 // I0 update ipsr.pp with psr.pp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) (pLvSys)mov r16=r0 // A clear r16 for leave_syscall, no-op otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) MOV_TO_IPSR(p0, r29, r25) // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mov ar.pfs=r26 // I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) (pLvSys)mov r17=r0 // A clear r17 for leave_syscall, no-op otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MOV_TO_IFS(p9, r30, r25)// M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) mov b0=r21 // I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) (pLvSys)mov r18=r0 // A clear r18 for leave_syscall, no-op otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) mov ar.fpsr=r20 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) MOV_TO_IIP(r28, r25) // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) nop 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) (pUStk) mov ar.rnat=r24 // M2 must happen with RSE in lazy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) nop 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) (pLvSys)mov r2=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mov ar.rsc=r27 // M2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mov pr=r31,-1 // I0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) RFI // B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * On entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * r20 = ¤t->thread_info->pre_count (if CONFIG_PREEMPTION)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * r31 = current->thread_info->flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * On exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * p6 = TRUE if work-pending-check needs to be redone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * Interrupts are disabled on entry, reenabled depend on work, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * disabled on exit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .work_pending_syscall:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) add r2=-8,r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) add r3=-8,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) st8 [r2]=r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) st8 [r3]=r10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) .work_pending:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) tbit.z p6,p0=r31,TIF_NEED_RESCHED // is resched not needed?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) (p6) br.cond.sptk.few .notify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) br.call.spnt.many rp=preempt_schedule_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .ret9: cmp.eq p6,p0=r0,r0 // p6 <- 1 (re-check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) (pLvSys)br.cond.sptk.few ia64_work_pending_syscall_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) br.cond.sptk.many .work_processed_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .notify:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) (pUStk) br.call.spnt.many rp=notify_resume_user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .ret10: cmp.ne p6,p0=r0,r0 // p6 <- 0 (don't re-check)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) (pLvSys)br.cond.sptk.few ia64_work_pending_syscall_end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) br.cond.sptk.many .work_processed_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .global ia64_work_pending_syscall_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ia64_work_pending_syscall_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) adds r2=PT(R8)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) adds r3=PT(R10)+16,r12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ld8 r8=[r2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ld8 r10=[r3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) br.cond.sptk.many ia64_work_processed_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) END(ia64_leave_kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ENTRY(handle_syscall_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * lead us to mistake a negative return value as a failed syscall. Those syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * must deposit a non-zero value in pt_regs.r8 to indicate an error. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) * pt_regs.r8 is zero, we assume that the call completed successfully.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ld8 r3=[r2] // load pt_regs.r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) cmp.eq p6,p7=r3,r0 // is pt_regs.r8==0?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) (p7) mov r10=-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) (p7) sub r8=0,r8 // negate return value to get errno
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) br.cond.sptk ia64_leave_syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) END(handle_syscall_error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * in case a system call gets restarted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GLOBAL_ENTRY(ia64_invoke_schedule_tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) alloc loc1=ar.pfs,8,2,1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) mov out0=r8 // Address of previous task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) br.call.sptk.many rp=schedule_tail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .ret11: mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) END(ia64_invoke_schedule_tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * Setup stack and call do_notify_resume_user(), keeping interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * Note that pSys and pNonSys need to be set up by the caller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * We declare 8 input registers so the system call args get preserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) * in case we need to restart a system call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) GLOBAL_ENTRY(notify_resume_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mov r9=ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mov loc0=rp // save return address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mov out0=0 // there is no "oldset"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) adds out1=8,sp // out1=&sigscratch->ar_pfs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) (pSys) mov out2=1 // out2==1 => we're in a syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) (pNonSys) mov out2=0 // out2==0 => not a syscall
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .fframe 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .spillsp ar.unat, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) st8 [sp]=r9,-16 // allocate space for ar.unat and save it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) st8 [out1]=loc1,-8 // save ar.pfs, out1=&sigscratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) br.call.sptk.many rp=do_notify_resume_user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .ret15: .restore sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) adds sp=16,sp // pop scratch stack space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ld8 r9=[sp] // load new unat from sigscratch->scratch_unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mov ar.unat=r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) END(notify_resume_user)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ENTRY(sys_rt_sigreturn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PT_REGS_UNWIND_INFO(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) * Allocate 8 input registers since ptrace() may clobber them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) alloc r2=ar.pfs,8,0,1,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PT_REGS_SAVES(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) adds sp=-16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) cmp.eq pNonSys,pSys=r0,r0 // sigreturn isn't a normal syscall...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * syscall-entry path does not save them we save them here instead. Note: we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * don't need to save any other registers that are not saved by the stream-lined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * syscall path, because restore_sigcontext() restores them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) adds r16=PT(F6)+32,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) adds r17=PT(F7)+32,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) stf.spill [r16]=f6,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) stf.spill [r17]=f7,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) stf.spill [r16]=f8,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) stf.spill [r17]=f9,32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) stf.spill [r16]=f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) stf.spill [r17]=f11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) adds out0=16,sp // out0 = &sigscratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) br.call.sptk.many rp=ia64_rt_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .ret19: .restore sp,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) adds sp=16,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ld8 r9=[sp] // load new ar.unat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mov.sptk b7=r8,ia64_leave_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) mov ar.unat=r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) br.many b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) END(sys_rt_sigreturn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .prologue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) mov r16=r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) DO_SAVE_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) br.call.sptk.many rp=ia64_handle_unaligned // stack frame setup in ivt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .ret21: .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) DO_LOAD_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) br.cond.sptk.many rp // goes to ia64_leave_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) END(ia64_prepare_handle_unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) // unw_init_running(void (*callback)(info, arg), void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) # define EXTRA_FRAME_SIZE ((UNW_FRAME_INFO_SIZE+15)&~15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) GLOBAL_ENTRY(unw_init_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) alloc loc1=ar.pfs,2,3,3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ld8 loc2=[in0],8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) mov loc0=rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mov r16=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) DO_SAVE_SWITCH_STACK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) adds sp=-EXTRA_FRAME_SIZE,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .body
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) adds out0=16,sp // &info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) mov out1=r13 // current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) adds out2=16+EXTRA_FRAME_SIZE,sp // &switch_stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) br.call.sptk.many rp=unw_init_frame_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) 1: adds out0=16,sp // &info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) mov b6=loc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) mov loc2=gp // save gp across indirect function call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ld8 gp=[in0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mov out1=in1 // arg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) br.call.sptk.many rp=b6 // invoke the callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) 1: mov gp=loc2 // restore gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) // For now, we don't allow changing registers from within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) // unw_init_running; if we ever want to allow that, we'd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) // have to do a load_switch_stack here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .restore sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) mov ar.pfs=loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) mov rp=loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) br.ret.sptk.many rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) END(unw_init_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) EXPORT_SYMBOL(unw_init_running)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #ifdef CONFIG_FUNCTION_TRACER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #ifdef CONFIG_DYNAMIC_FTRACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) GLOBAL_ENTRY(_mcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) br ftrace_stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) END(_mcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) EXPORT_SYMBOL(_mcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) br.ret.sptk.many b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) GLOBAL_ENTRY(ftrace_caller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) alloc out0 = ar.pfs, 8, 0, 4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) mov out3 = r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) mov out2 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) add r3 = 0x20, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) mov out1 = r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) br.call.sptk.many b0 = ftrace_patch_gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) //this might be called from module, so we must patch gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ftrace_patch_gp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) movl gp=__gp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mov b0 = r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .global ftrace_call;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ftrace_call:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .mlx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) nop.m 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) movl r3 = .here;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) alloc loc0 = ar.pfs, 4, 4, 2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) mov loc1 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) mov out0 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) mov loc2 = r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) mov loc3 = r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) adds out0 = -MCOUNT_INSN_SIZE, out0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) mov out1 = in2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) mov b6 = r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) br.call.sptk.many b0 = b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) mov ar.pfs = loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) mov b0 = loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) mov r8 = loc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) mov r15 = loc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) br ftrace_stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) END(ftrace_caller)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) GLOBAL_ENTRY(_mcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) movl r2 = ftrace_stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) movl r3 = ftrace_trace_function;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ld8 r3 = [r3];;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ld8 r3 = [r3];;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) cmp.eq p7,p0 = r2, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) (p7) br.sptk.many ftrace_stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) alloc loc0 = ar.pfs, 4, 4, 2, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mov loc1 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) mov out0 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mov loc2 = r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) mov loc3 = r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) adds out0 = -MCOUNT_INSN_SIZE, out0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mov out1 = in2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) mov b6 = r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) br.call.sptk.many b0 = b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) mov ar.pfs = loc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) mov b0 = loc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) mov r8 = loc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) mov r15 = loc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) br ftrace_stub
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) END(_mcount)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) GLOBAL_ENTRY(ftrace_stub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mov r3 = b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) movl r2 = _mcount_ret_helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ;;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mov b6 = r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) mov b7 = r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) br.ret.sptk.many b6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) _mcount_ret_helper:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) mov b0 = r42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) mov r1 = r41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mov ar.pfs = r40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) br b7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) END(ftrace_stub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #endif /* CONFIG_FUNCTION_TRACER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define __SYSCALL(nr, entry, nargs) data8 entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .rodata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .align 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .globl sys_call_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) sys_call_table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #include <asm/syscall_table.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #undef __SYSCALL
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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