^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/timex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clocksource.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* IBM Summit (EXA) Cyclone counter code*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CYCLONE_CBAR_ADDR 0xFEB00CD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CYCLONE_PMCC_OFFSET 0x51A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CYCLONE_MPMC_OFFSET 0x51D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CYCLONE_MPCS_OFFSET 0x51A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CYCLONE_TIMER_FREQ 100000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int use_cyclone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) void __init cyclone_setup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) use_cyclone = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void __iomem *cyclone_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static u64 read_cyclone(struct clocksource *cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) return (u64)readq((void __iomem *)cyclone_mc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static struct clocksource clocksource_cyclone = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .name = "cyclone",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .rating = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .read = read_cyclone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .mask = (1LL << 40) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .flags = CLOCK_SOURCE_IS_CONTINUOUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int __init init_cyclone_clock(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u64 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u64 base; /* saved cyclone base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u64 offset; /* offset from pageaddr to cyclone_timer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 __iomem *cyclone_timer; /* Cyclone MPMC0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!use_cyclone)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* find base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) offset = (CYCLONE_CBAR_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) reg = ioremap(offset, sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if(!reg){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) " register.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) base = readq(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if(!base){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) " value.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* setup PMCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) offset = (base + CYCLONE_PMCC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg = ioremap(offset, sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if(!reg){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) printk(KERN_ERR "Summit chipset: Could not find valid PMCC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) " register.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) writel(0x00000001,reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* setup MPCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) offset = (base + CYCLONE_MPCS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = ioremap(offset, sizeof(u64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if(!reg){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) printk(KERN_ERR "Summit chipset: Could not find valid MPCS"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) " register.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) writel(0x00000001,reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) iounmap(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* map in cyclone_timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) offset = (base + CYCLONE_MPMC_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) cyclone_timer = ioremap(offset, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if(!cyclone_timer){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) printk(KERN_ERR "Summit chipset: Could not find valid MPMC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) " register.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*quick test to make sure its ticking*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for(i=0; i<3; i++){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 old = readl(cyclone_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int stall = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) while(stall--) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if(readl(cyclone_timer) == old){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) printk(KERN_ERR "Summit chipset: Counter not counting!"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) " DISABLED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) iounmap(cyclone_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cyclone_timer = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) use_cyclone = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* initialize last tick */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) cyclone_mc = cyclone_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) clocksource_cyclone.archdata.fsys_mmio = cyclone_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) clocksource_register_hz(&clocksource_cyclone, CYCLONE_TIMER_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __initcall(init_cyclone_clock);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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