^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_IA64_SAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_IA64_SAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * System Abstraction Layer definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This is based on version 2.5 of the manual "IA-64 System
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Abstraction Layer".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2001 Intel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2002 Jenna Hall <jenna.s.hall@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2001 Fred Lewis <frederick.v.lewis@intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1998, 1999, 2001, 2003 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * 02/01/04 J. Hall Updated Error Record Structures to conform to July 2001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * revision of the SAL spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 01/01/03 fvlewis Updated Error Record Structures to conform with Nov. 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * revision of the SAL spec.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 99/09/29 davidm Updated for SAL 2.6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 00/03/29 cfleck Updated SAL Error Logging info for processor (SAL 2.6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * (plus examples of platform error info structures from smariset @ Intel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IA64_SAL_PLATFORM_FEATURE_BUS_LOCK (1<<IA64_SAL_PLATFORM_FEATURE_BUS_LOCK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IRQ_REDIR_HINT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT (1<<IA64_SAL_PLATFORM_FEATURE_IPI_REDIR_HINT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT (1<<IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/bcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/efi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/pal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) extern unsigned long sal_systab_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern spinlock_t sal_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* SAL spec _requires_ eight args for each call. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define __IA64_FW_CALL(entry,result,a0,a1,a2,a3,a4,a5,a6,a7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) result = (*entry)(a0,a1,a2,a3,a4,a5,a6,a7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define IA64_FW_CALL(entry,result,args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned long __ia64_sc_flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct ia64_fpreg __ia64_sc_fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ia64_save_scratch_fpregs(__ia64_sc_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) spin_lock_irqsave(&sal_lock, __ia64_sc_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) __IA64_FW_CALL(entry, result, args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) spin_unlock_irqrestore(&sal_lock, __ia64_sc_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ia64_load_scratch_fpregs(__ia64_sc_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define SAL_CALL(result,args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) IA64_FW_CALL(ia64_sal, result, args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define SAL_CALL_NOLOCK(result,args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned long __ia64_scn_flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct ia64_fpreg __ia64_scn_fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ia64_save_scratch_fpregs(__ia64_scn_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) local_irq_save(__ia64_scn_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) __IA64_FW_CALL(ia64_sal, result, args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) local_irq_restore(__ia64_scn_flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ia64_load_scratch_fpregs(__ia64_scn_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define SAL_CALL_REENTRANT(result,args...) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct ia64_fpreg __ia64_scs_fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ia64_save_scratch_fpregs(__ia64_scs_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) preempt_disable(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) __IA64_FW_CALL(ia64_sal, result, args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) preempt_enable(); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ia64_load_scratch_fpregs(__ia64_scs_fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAL_SET_VECTORS 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAL_GET_STATE_INFO 0x01000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAL_GET_STATE_INFO_SIZE 0x01000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SAL_CLEAR_STATE_INFO 0x01000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SAL_MC_RENDEZ 0x01000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SAL_MC_SET_PARAMS 0x01000005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SAL_REGISTER_PHYSICAL_ADDR 0x01000006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SAL_CACHE_FLUSH 0x01000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SAL_CACHE_INIT 0x01000009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SAL_PCI_CONFIG_READ 0x01000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SAL_PCI_CONFIG_WRITE 0x01000011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SAL_FREQ_BASE 0x01000012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SAL_PHYSICAL_ID_INFO 0x01000013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SAL_UPDATE_PAL 0x01000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct ia64_sal_retval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * A zero status value indicates call completed without error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * A negative status value indicates reason of call failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * A positive status value indicates success but an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * informational value should be printed (e.g., "reboot for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * change to take effect").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) long status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned long v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned long v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) typedef struct ia64_sal_retval (*ia64_sal_handler) (u64, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) SAL_FREQ_BASE_PLATFORM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) SAL_FREQ_BASE_INTERVAL_TIMER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SAL_FREQ_BASE_REALTIME_CLOCK = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * The SAL system table is followed by a variable number of variable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * length descriptors. The structure of these descriptors follows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * The defininition follows SAL specs from July 2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct ia64_sal_systab {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 signature[4]; /* should be "SST_" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 size; /* size of this table in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 sal_rev_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 sal_rev_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 entry_count; /* # of entries in variable portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 reserved1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 sal_a_rev_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u8 sal_a_rev_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u8 sal_b_rev_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u8 sal_b_rev_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* oem_id & product_id: terminating NUL is missing if string is exactly 32 bytes long. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 oem_id[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 product_id[32]; /* ASCII product id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u8 reserved2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) enum sal_systab_entry_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) SAL_DESC_ENTRY_POINT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SAL_DESC_MEMORY = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SAL_DESC_PLATFORM_FEATURE = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SAL_DESC_TR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SAL_DESC_PTC = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SAL_DESC_AP_WAKEUP = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Entry type: Size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * 0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * 1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * 3 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * 4 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * 5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SAL_DESC_SIZE(type) "\060\040\020\040\020\020"[(unsigned) type]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) typedef struct ia64_sal_desc_entry_point {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 reserved1[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u64 pal_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u64 sal_proc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u64 gp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 reserved2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }ia64_sal_desc_entry_point_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) typedef struct ia64_sal_desc_memory {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u8 used_by_sal; /* needs to be mapped for SAL? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u8 mem_attr; /* current memory attribute setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 access_rights; /* access rights set up by SAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 mem_attr_mask; /* mask of supported memory attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u8 reserved1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u8 mem_type; /* memory type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 mem_usage; /* memory usage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u64 addr; /* physical address of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 length; /* length (multiple of 4KB pages) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 reserved2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 oem_reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } ia64_sal_desc_memory_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) typedef struct ia64_sal_desc_platform_feature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 feature_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 reserved1[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } ia64_sal_desc_platform_feature_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) typedef struct ia64_sal_desc_tr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u8 tr_type; /* 0 == instruction, 1 == data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u8 regnum; /* translation register number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u8 reserved1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u64 addr; /* virtual address of area covered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u64 page_size; /* encoded page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 reserved2[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) } ia64_sal_desc_tr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) typedef struct ia64_sal_desc_ptc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 reserved1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 num_domains; /* # of coherence domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u64 domain_info; /* physical address of domain info table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } ia64_sal_desc_ptc_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) typedef struct ia64_sal_ptc_domain_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u64 proc_count; /* number of processors in domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u64 proc_list; /* physical address of LID array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } ia64_sal_ptc_domain_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) typedef struct ia64_sal_ptc_domain_proc_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u64 id : 8; /* id of processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u64 eid : 8; /* eid of processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } ia64_sal_ptc_domain_proc_entry_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IA64_SAL_AP_EXTERNAL_INT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) typedef struct ia64_sal_desc_ap_wakeup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u8 mechanism; /* 0 == external interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 reserved1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u64 vector; /* interrupt vector in range 0x10-0xff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) } ia64_sal_desc_ap_wakeup_t ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) extern ia64_sal_handler ia64_sal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) extern struct ia64_sal_desc_ptc *ia64_ptc_domain_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) extern unsigned short sal_revision; /* supported SAL spec revision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) extern unsigned short sal_version; /* SAL version; OEM dependent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SAL_VERSION_CODE(major, minor) ((bin2bcd(major) << 8) | bin2bcd(minor))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) extern const char *ia64_sal_strerror (long status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) extern void ia64_sal_init (struct ia64_sal_systab *sal_systab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* SAL information type encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SAL_INFO_TYPE_MCA = 0, /* Machine check abort information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SAL_INFO_TYPE_INIT = 1, /* Init information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) SAL_INFO_TYPE_CMC = 2, /* Corrected machine check information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SAL_INFO_TYPE_CPE = 3 /* Corrected platform error information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Encodings for machine check parameter types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) SAL_MC_PARAM_RENDEZ_INT = 1, /* Rendezvous interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) SAL_MC_PARAM_RENDEZ_WAKEUP = 2, /* Wakeup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) SAL_MC_PARAM_CPE_INT = 3 /* Corrected Platform Error Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Encodings for rendezvous mechanisms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) SAL_MC_PARAM_MECHANISM_INT = 1, /* Use interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SAL_MC_PARAM_MECHANISM_MEM = 2 /* Use memory synchronization variable*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Encodings for vectors which can be registered by the OS with SAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) SAL_VECTOR_OS_MCA = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) SAL_VECTOR_OS_INIT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) SAL_VECTOR_OS_BOOT_RENDEZ = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Encodings for mca_opt parameter sent to SAL_MC_SET_PARAMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SAL_MC_PARAM_RZ_ALWAYS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define SAL_MC_PARAM_BINIT_ESCALATE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Definition of the SAL Error Log from the SAL spec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* SAL Error Record Section GUID Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SAL_PROC_DEV_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) EFI_GUID(0xe429faf1, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SAL_PLAT_MEM_DEV_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EFI_GUID(0xe429faf2, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SAL_PLAT_SEL_DEV_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EFI_GUID(0xe429faf3, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SAL_PLAT_PCI_BUS_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) EFI_GUID(0xe429faf4, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SAL_PLAT_SMBIOS_DEV_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EFI_GUID(0xe429faf5, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SAL_PLAT_PCI_COMP_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EFI_GUID(0xe429faf6, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SAL_PLAT_SPECIFIC_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EFI_GUID(0xe429faf7, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SAL_PLAT_HOST_CTLR_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SAL_PLAT_BUS_ERR_SECT_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0xca, 0x4d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MAX_CACHE_ERRORS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MAX_TLB_ERRORS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MAX_BUS_ERRORS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Definition of version according to SAL spec for logging purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) typedef struct sal_log_revision {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u8 minor; /* BCD (0..99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u8 major; /* BCD (0..99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } sal_log_revision_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Definition of timestamp according to SAL spec for logging purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) typedef struct sal_log_timestamp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 slh_second; /* Second (0..59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u8 slh_minute; /* Minute (0..59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u8 slh_hour; /* Hour (0..23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u8 slh_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 slh_day; /* Day (1..31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 slh_month; /* Month (1..12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u8 slh_year; /* Year (00..99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 slh_century; /* Century (19, 20, 21, ...) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) } sal_log_timestamp_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Definition of log record header structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) typedef struct sal_log_record_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u64 id; /* Unique monotonically increasing ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) sal_log_revision_t revision; /* Major and Minor revision of header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 severity; /* Error Severity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 validation_bits; /* 0: platform_guid, 1: !timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) u32 len; /* Length of this error log in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sal_log_timestamp_t timestamp; /* Timestamp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) efi_guid_t platform_guid; /* Unique OEM Platform ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } sal_log_record_header_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define sal_log_severity_recoverable 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define sal_log_severity_fatal 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define sal_log_severity_corrected 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * Error Recovery Info (ERI) bit decode. From SAL Spec section B.2.2 Table B-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * Error Section Error_Recovery_Info Field Definition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define ERI_NOT_VALID 0x0 /* Error Recovery Field is not valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define ERI_NOT_ACCESSIBLE 0x30 /* Resource not accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define ERI_CONTAINMENT_WARN 0x22 /* Corrupt data propagated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ERI_UNCORRECTED_ERROR 0x20 /* Uncorrected error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define ERI_COMPONENT_RESET 0x24 /* Component must be reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ERI_CORR_ERROR_LOG 0x21 /* Corrected error, needs logging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ERI_CORR_ERROR_THRESH 0x29 /* Corrected error threshold exceeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* Definition of log section header structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) typedef struct sal_log_sec_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) efi_guid_t guid; /* Unique Section ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) sal_log_revision_t revision; /* Major and Minor revision of Section */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 error_recovery_info; /* Platform error recovery status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 len; /* Section length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) } sal_log_section_hdr_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) typedef struct sal_log_mod_error_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u64 check_info : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) requestor_identifier : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) responder_identifier : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) target_identifier : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) precise_ip : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reserved : 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u64 check_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u64 requestor_identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u64 responder_identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u64 target_identifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u64 precise_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } sal_log_mod_error_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) typedef struct sal_processor_static_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u64 minstate : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) br : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cr : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ar : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rr : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fr : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) reserved : 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) pal_min_state_area_t min_state_area;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u64 br[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u64 cr[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u64 ar[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u64 rr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct ia64_fpreg __attribute__ ((packed)) fr[128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } sal_processor_static_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct sal_cpuid_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u64 regs[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u64 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) typedef struct sal_log_processor_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u64 proc_error_map : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) proc_state_param : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) proc_cr_lid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) psi_static_struct : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) num_cache_check : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) num_tlb_check : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) num_bus_check : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) num_reg_file_check : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) num_ms_check : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) cpuid_info : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) reserved1 : 39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u64 proc_error_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u64 proc_state_parameter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) u64 proc_cr_lid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * The rest of this structure consists of variable-length arrays, which can't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * expressed in C.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) sal_log_mod_error_info_t info[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * This is what the rest looked like if C supported variable-length arrays:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * sal_log_mod_error_info_t cache_check_info[.valid.num_cache_check];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * sal_log_mod_error_info_t tlb_check_info[.valid.num_tlb_check];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * sal_log_mod_error_info_t bus_check_info[.valid.num_bus_check];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * sal_log_mod_error_info_t reg_file_check_info[.valid.num_reg_file_check];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * sal_log_mod_error_info_t ms_check_info[.valid.num_ms_check];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * struct sal_cpuid_info cpuid_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * sal_processor_static_info_t processor_static_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } sal_log_processor_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Given a sal_log_processor_info_t pointer, return a pointer to the processor_static_info: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SAL_LPI_PSI_INFO(l) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ({ sal_log_processor_info_t *_l = (l); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ((sal_processor_static_info_t *) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ((char *) _l->info + ((_l->valid.num_cache_check + _l->valid.num_tlb_check \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) + _l->valid.num_bus_check + _l->valid.num_reg_file_check \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) + _l->valid.num_ms_check) * sizeof(sal_log_mod_error_info_t) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) + sizeof(struct sal_cpuid_info)))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* platform error log structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) typedef struct sal_log_mem_dev_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) u64 error_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) physical_addr : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) addr_mask : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) node : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) card : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) module : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) bank : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) device : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) row : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) column : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bit_position : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) requestor_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) responder_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) target_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) bus_spec_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) oem_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) reserved : 47;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u64 error_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u64 physical_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u64 addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u16 node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u16 card;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u16 module;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u16 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u16 device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u16 row;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u16 column;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u16 bit_position;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u64 requestor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u64 responder_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u64 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u64 bus_spec_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 oem_id[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u8 oem_data[1]; /* Variable length data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) } sal_log_mem_dev_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) typedef struct sal_log_sel_dev_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u64 record_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) record_type : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) generator_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) evm_rev : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sensor_type : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) sensor_num : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) event_dir : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) event_data1 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) event_data2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) event_data3 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) reserved : 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u16 record_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 record_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 timestamp[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u16 generator_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u8 evm_rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u8 sensor_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 sensor_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u8 event_dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u8 event_data1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 event_data2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) u8 event_data3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } sal_log_sel_dev_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) typedef struct sal_log_pci_bus_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u64 err_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) err_type : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) bus_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) bus_address : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) bus_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) bus_cmd : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) requestor_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) responder_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) target_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) reserved : 54;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u64 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u16 err_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u16 bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u64 bus_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u64 bus_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u64 bus_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u64 requestor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u64 responder_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u64 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 oem_data[1]; /* Variable length data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) } sal_log_pci_bus_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) typedef struct sal_log_smbios_dev_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u64 event_type : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) length : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) time_stamp : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) reserved1 : 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u8 event_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u8 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u8 time_stamp[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 data[1]; /* data of variable length, length == slsmb_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) } sal_log_smbios_dev_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) typedef struct sal_log_pci_comp_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u64 err_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) comp_info : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) num_mem_regs : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) num_io_regs : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) reg_data_pairs : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reserved : 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u64 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u16 vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u16 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u8 class_code[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u8 func_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) u8 dev_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) u8 bus_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u8 seg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u8 reserved[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) } comp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) u32 num_mem_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 num_io_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u64 reg_data_pairs[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) * array of address/data register pairs is num_mem_regs + num_io_regs elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) * long. Each array element consists of a u64 address followed by a u64 data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * value. The oem_data array immediately follows the reg_data_pairs array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 oem_data[1]; /* Variable length data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) } sal_log_pci_comp_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) typedef struct sal_log_plat_specific_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u64 err_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) guid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) reserved : 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u64 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) efi_guid_t guid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u8 oem_data[1]; /* platform specific variable length data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } sal_log_plat_specific_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) typedef struct sal_log_host_ctlr_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u64 err_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) requestor_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) responder_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) target_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) bus_spec_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reserved : 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u64 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u64 requestor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) u64 responder_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u64 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u64 bus_spec_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 oem_data[1]; /* Variable length OEM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } sal_log_host_ctlr_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) typedef struct sal_log_plat_bus_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) sal_log_section_hdr_t header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u64 err_status : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) requestor_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) responder_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) target_id : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bus_spec_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) oem_data : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) reserved : 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u64 err_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u64 requestor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u64 responder_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u64 target_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u64 bus_spec_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u8 oem_data[1]; /* Variable length OEM data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } sal_log_plat_bus_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* Overall platform error section structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) typedef union sal_log_platform_err_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) sal_log_mem_dev_err_info_t mem_dev_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) sal_log_sel_dev_err_info_t sel_dev_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) sal_log_pci_bus_err_info_t pci_bus_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) sal_log_smbios_dev_err_info_t smbios_dev_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) sal_log_pci_comp_err_info_t pci_comp_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) sal_log_plat_specific_err_info_t plat_specific_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) sal_log_host_ctlr_err_info_t host_ctlr_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) sal_log_plat_bus_err_info_t plat_bus_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } sal_log_platform_err_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* SAL log over-all, multi-section error record structure (processor+platform) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) typedef struct err_rec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) sal_log_record_header_t sal_elog_header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) sal_log_processor_info_t proc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) sal_log_platform_err_info_t plat_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u8 oem_data_pad[1024];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } ia64_err_rec_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Now define a couple of inline functions for improved type checking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * and convenience.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) extern s64 ia64_sal_cache_flush (u64 cache_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) extern void __init check_sal_cache_flush (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /* Initialize all the processor and platform level instruction and data caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ia64_sal_cache_init (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) SAL_CALL(isrv, SAL_CACHE_INIT, 0, 0, 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * Clear the processor and platform information logged by SAL with respect to the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * state at the time of MCA's, INITs, CMCs, or CPEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ia64_sal_clear_state_info (u64 sal_info_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) SAL_CALL_REENTRANT(isrv, SAL_CLEAR_STATE_INFO, sal_info_type, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Get the processor and platform information logged by SAL with respect to the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * state at the time of the MCAs, INITs, CMCs, or CPEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static inline u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ia64_sal_get_state_info (u64 sal_info_type, u64 *sal_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO, sal_info_type, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sal_info, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (isrv.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return isrv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Get the maximum size of the information logged by SAL with respect to the machine state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * at the time of MCAs, INITs, CMCs, or CPEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static inline u64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ia64_sal_get_state_info_size (u64 sal_info_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SAL_CALL_REENTRANT(isrv, SAL_GET_STATE_INFO_SIZE, sal_info_type, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (isrv.status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return isrv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * Causes the processor to go into a spin loop within SAL where SAL awaits a wakeup from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * the monarch processor. Must not lock, because it will not return on any cpu until the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) * monarch processor sends a wake up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ia64_sal_mc_rendez (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) SAL_CALL_NOLOCK(isrv, SAL_MC_RENDEZ, 0, 0, 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * Allow the OS to specify the interrupt number to be used by SAL to interrupt OS during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * the machine check rendezvous sequence as well as the mechanism to wake up the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * non-monarch processor at the end of machine check processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Returns the complete ia64_sal_retval because some calls return more than just a status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static inline struct ia64_sal_retval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ia64_sal_mc_set_params (u64 param_type, u64 i_or_m, u64 i_or_m_val, u64 timeout, u64 rz_always)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SAL_CALL(isrv, SAL_MC_SET_PARAMS, param_type, i_or_m, i_or_m_val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) timeout, rz_always, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* Read from PCI configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ia64_sal_pci_config_read (u64 pci_config_addr, int type, u64 size, u64 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SAL_CALL(isrv, SAL_PCI_CONFIG_READ, pci_config_addr, size, type, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *value = isrv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* Write to PCI configuration space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ia64_sal_pci_config_write (u64 pci_config_addr, int type, u64 size, u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) SAL_CALL(isrv, SAL_PCI_CONFIG_WRITE, pci_config_addr, size, value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) type, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * Register physical addresses of locations needed by SAL when SAL procedures are invoked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * in virtual mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ia64_sal_register_physical_addr (u64 phys_entry, u64 phys_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SAL_CALL(isrv, SAL_REGISTER_PHYSICAL_ADDR, phys_entry, phys_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Register software dependent code locations within SAL. These locations are handlers or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * entry points where SAL will pass control for the specified event. These event handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * are for the bott rendezvous, MCAs and INIT scenarios.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ia64_sal_set_vectors (u64 vector_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u64 handler_addr1, u64 gp1, u64 handler_len1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u64 handler_addr2, u64 gp2, u64 handler_len2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) SAL_CALL(isrv, SAL_SET_VECTORS, vector_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) handler_addr1, gp1, handler_len1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) handler_addr2, gp2, handler_len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Update the contents of PAL block in the non-volatile storage device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u64 *error_code, u64 *scratch_buf_size_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) SAL_CALL(isrv, SAL_UPDATE_PAL, param_buf, scratch_buf, scratch_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (error_code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) *error_code = isrv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (scratch_buf_size_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) *scratch_buf_size_needed = isrv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* Get physical processor die mapping in the platform. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ia64_sal_physical_id_info(u16 *splid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct ia64_sal_retval isrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (sal_revision < SAL_VERSION_CODE(3,2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (splid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) *splid = isrv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return isrv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) extern unsigned long sal_platform_features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct sal_ret_values {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) long r8; long r9; long r10; long r11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define IA64_SAL_OEMFUNC_MIN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define IA64_SAL_OEMFUNC_MAX 0x03ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) extern int ia64_sal_oemcall(struct ia64_sal_retval *, u64, u64, u64, u64, u64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64, u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u64, u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) extern long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ia64_sal_freq_base (unsigned long which, unsigned long *ticks_per_second,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned long *drift_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * System Abstraction Layer Specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * Note: region regs are stored first in head.S _start. Hence they must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * stay up front.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct sal_to_os_boot {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u64 rr[8]; /* Region Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u64 br[6]; /* br0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * return addr into SAL boot rendez routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u64 gr1; /* SAL:GP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u64 gr12; /* SAL:SP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u64 gr13; /* SAL: Task Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u64 fpsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u64 pfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u64 rnat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u64 unat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u64 bspstore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u64 dcr; /* Default Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u64 iva;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u64 pta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u64 itv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u64 pmv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u64 cmcv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u64 lrr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u64 gr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u64 pr; /* Predicate registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u64 lc; /* Loop Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct ia64_fpreg fp[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * Global array allocated for NR_CPUS at boot time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) extern void ia64_jump_to_sal(struct sal_to_os_boot *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) extern void ia64_sal_handler_init(void *entry_point, void *gpval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define PALO_MAX_TLB_PURGES 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define PALO_SIG "PALO"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct palo_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u8 signature[4]; /* Should be "PALO" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u8 minor_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u8 major_revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u8 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u8 reserved1[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u16 max_tlb_purges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u8 reserved2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define NPTCG_FROM_PAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define NPTCG_FROM_PALO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define NPTCG_FROM_KERNEL_PARAMETER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #endif /* _ASM_IA64_SAL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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