^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_IA64_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_IA64_PGTABLE_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file contains the functions and defines necessary to modify and use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * the IA-64 page table tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This hopefully works with any (fixed) IA-64 page-size, as defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * in <asm/page.h>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1998-2005 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IA64_MAX_PHYS_BITS 50 /* max. number of physical address bits (architected) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * First, define the various bits in a PTE. Note that the PTE format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * matches the VHPT short format, the firt doubleword of the VHPD long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * format, and the first doubleword of the TLB insertion format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define _PAGE_P_BIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define _PAGE_A_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define _PAGE_D_BIT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define _PAGE_P (1 << _PAGE_P_BIT) /* page present bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define _PAGE_MA_WB (0x0 << 2) /* write back memory attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define _PAGE_MA_UC (0x4 << 2) /* uncacheable memory attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define _PAGE_MA_UCE (0x5 << 2) /* UC exported attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define _PAGE_MA_WC (0x6 << 2) /* write coalescing memory attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define _PAGE_MA_NAT (0x7 << 2) /* not-a-thing attribute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define _PAGE_MA_MASK (0x7 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define _PAGE_PL_0 (0 << 7) /* privilege level 0 (kernel) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define _PAGE_PL_1 (1 << 7) /* privilege level 1 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define _PAGE_PL_2 (2 << 7) /* privilege level 2 (unused) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define _PAGE_PL_3 (3 << 7) /* privilege level 3 (user) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define _PAGE_PL_MASK (3 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define _PAGE_AR_R (0 << 9) /* read only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define _PAGE_AR_RX (1 << 9) /* read & execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define _PAGE_AR_RW (2 << 9) /* read & write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define _PAGE_AR_RWX (3 << 9) /* read, write & execute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define _PAGE_AR_R_RW (4 << 9) /* read / read & write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define _PAGE_AR_RX_RWX (5 << 9) /* read & exec / read, write & exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define _PAGE_AR_RWX_RW (6 << 9) /* read, write & exec / read & write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define _PAGE_AR_X_RX (7 << 9) /* exec & promote / read & exec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define _PAGE_AR_MASK (7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define _PAGE_AR_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define _PAGE_A (1 << _PAGE_A_BIT) /* page accessed bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define _PAGE_D (1 << _PAGE_D_BIT) /* page dirty bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define _PAGE_PPN_MASK (((__IA64_UL(1) << IA64_MAX_PHYS_BITS) - 1) & ~0xfffUL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define _PAGE_ED (__IA64_UL(1) << 52) /* exception deferral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define _PAGE_PROTNONE (__IA64_UL(1) << 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define _PFN_MASK _PAGE_PPN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Mask of bits which may be changed by pte_modify(); the odd bits are there for _PAGE_PROTNONE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define _PAGE_CHG_MASK (_PAGE_P | _PAGE_PROTNONE | _PAGE_PL_MASK | _PAGE_AR_MASK | _PAGE_ED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define _PAGE_SIZE_4K 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define _PAGE_SIZE_8K 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define _PAGE_SIZE_16K 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define _PAGE_SIZE_64K 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define _PAGE_SIZE_256K 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define _PAGE_SIZE_1M 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define _PAGE_SIZE_4M 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define _PAGE_SIZE_16M 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define _PAGE_SIZE_64M 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define _PAGE_SIZE_256M 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define _PAGE_SIZE_1G 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define _PAGE_SIZE_4G 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define __ACCESS_BITS _PAGE_ED | _PAGE_A | _PAGE_P | _PAGE_MA_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define __DIRTY_BITS_NO_ED _PAGE_A | _PAGE_P | _PAGE_D | _PAGE_MA_WB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define __DIRTY_BITS _PAGE_ED | __DIRTY_BITS_NO_ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * How many pointers will a page table level hold expressed in shift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PTRS_PER_PTD_SHIFT (PAGE_SHIFT-3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Definitions for fourth level:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PTRS_PER_PTE (__IA64_UL(1) << (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Definitions for third level:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * PMD_SHIFT determines the size of the area a third-level page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * can map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PMD_SHIFT (PAGE_SHIFT + (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PMD_SIZE (1UL << PMD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMD_MASK (~(PMD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PTRS_PER_PMD (1UL << (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #if CONFIG_PGTABLE_LEVELS == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Definitions for second level:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * PUD_SHIFT determines the size of the area a second-level page table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * can map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PUD_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PUD_SIZE (1UL << PUD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PUD_MASK (~(PUD_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PTRS_PER_PUD (1UL << (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * Definitions for first level:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * PGDIR_SHIFT determines what a first-level page table entry can map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #if CONFIG_PGTABLE_LEVELS == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PGDIR_SHIFT (PUD_SHIFT + (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PGDIR_SHIFT (PMD_SHIFT + (PTRS_PER_PTD_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PGDIR_SIZE (__IA64_UL(1) << PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PGDIR_MASK (~(PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PTRS_PER_PGD_SHIFT PTRS_PER_PTD_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PTRS_PER_PGD (1UL << PTRS_PER_PGD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USER_PTRS_PER_PGD (5*PTRS_PER_PGD/8) /* regions 0-4 are user regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FIRST_USER_ADDRESS 0UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * All the normal masks have the "page accessed" bits on, as any time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * they are used, the page is accessed. They are cleared only by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * page-out routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PAGE_SHARED __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PAGE_READONLY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PAGE_COPY __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_R)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PAGE_COPY_EXEC __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PAGE_GATE __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_X_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PAGE_KERNEL __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PAGE_KERNELRX __pgprot(__ACCESS_BITS | _PAGE_PL_0 | _PAGE_AR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PAGE_KERNEL_UC __pgprot(__DIRTY_BITS | _PAGE_PL_0 | _PAGE_AR_RWX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) _PAGE_MA_UC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) # ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #include <linux/sched/mm.h> /* for mm_struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * Next come the mappings that determine how mmap() protection bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * (PROT_EXEC, PROT_READ, PROT_WRITE, PROT_NONE) get implemented. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * _P version gets used for a private shared memory segment, the _S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * version gets used for a shared memory segment with MAP_SHARED on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * In a private shared memory segment, we do a copy-on-write if a task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * attempts to write to the page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* xwr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define __P000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define __P001 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define __P010 PAGE_READONLY /* write to priv pg -> copy & make writable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define __P011 PAGE_READONLY /* ditto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define __P100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define __P101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define __P110 PAGE_COPY_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define __P111 PAGE_COPY_EXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define __S000 PAGE_NONE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define __S001 PAGE_READONLY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define __S010 PAGE_SHARED /* we don't have (and don't need) write-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define __S011 PAGE_SHARED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define __S100 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_X_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define __S101 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define __S110 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define __S111 __pgprot(__ACCESS_BITS | _PAGE_PL_3 | _PAGE_AR_RWX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define pgd_ERROR(e) printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #if CONFIG_PGTABLE_LEVELS == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define pud_ERROR(e) printk("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define pmd_ERROR(e) printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define pte_ERROR(e) printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * Some definitions to translate between mem_map, PTEs, and page addresses:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Quick test to see if ADDR is a (potentially) valid physical address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ia64_phys_addr_valid (unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return (addr & (local_cpu_data->unimpl_pa_mask)) == 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * kern_addr_valid(ADDR) tests if ADDR is pointing to valid kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * memory. For the return value to be meaningful, ADDR must be >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * PAGE_OFFSET. This operation can be relatively expensive (e.g.,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * require a hash-, or multi-level tree-lookup or something of that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * sort) but it guarantees to return TRUE only if accessing the page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * at that address does not cause an error. Note that there may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * addresses for which kern_addr_valid() returns FALSE even though an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * access would not cause an error (e.g., this is typically true for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * memory mapped I/O regions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * XXX Need to implement this for IA-64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define kern_addr_valid(addr) (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Now come the defines and routines to manage and access the three-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * page table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define VMALLOC_START (RGN_BASE(RGN_GATE) + 0x200000000UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #ifdef CONFIG_VIRTUAL_MEM_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) # define VMALLOC_END_INIT (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) extern unsigned long VMALLOC_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #if defined(CONFIG_SPARSEMEM) && defined(CONFIG_SPARSEMEM_VMEMMAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* SPARSEMEM_VMEMMAP uses half of vmalloc... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) # define vmemmap ((struct page *)VMALLOC_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) # define VMALLOC_END (RGN_BASE(RGN_GATE) + (1UL << (4*PAGE_SHIFT - 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* fs/proc/kcore.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define kc_vaddr_to_offset(v) ((v) - RGN_BASE(RGN_GATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define kc_offset_to_vaddr(o) ((o) + RGN_BASE(RGN_GATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define RGN_MAP_SHIFT (PGDIR_SHIFT + PTRS_PER_PGD_SHIFT - 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define RGN_MAP_LIMIT ((1UL << RGN_MAP_SHIFT) - PAGE_SIZE) /* per region addr limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Conversion functions: convert page frame number (pfn) and a protection value to a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * table entry (pte).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define pfn_pte(pfn, pgprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ({ pte_t __pte; pte_val(__pte) = ((pfn) << PAGE_SHIFT) | pgprot_val(pgprot); __pte; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Extract pfn from pte. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define pte_pfn(_pte) ((pte_val(_pte) & _PFN_MASK) >> PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* This takes a physical page address that is used by the remapping functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define mk_pte_phys(physpage, pgprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define pte_modify(_pte, newprot) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (__pte((pte_val(_pte) & ~_PAGE_CHG_MASK) | (pgprot_val(newprot) & _PAGE_CHG_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define pte_none(pte) (!pte_val(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define pte_present(pte) (pte_val(pte) & (_PAGE_P | _PAGE_PROTNONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define pte_clear(mm,addr,pte) (pte_val(*(pte)) = 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* pte_page() returns the "struct page *" corresponding to the PTE: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define pte_page(pte) virt_to_page(((pte_val(pte) & _PFN_MASK) + PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define pmd_none(pmd) (!pmd_val(pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define pmd_bad(pmd) (!ia64_phys_addr_valid(pmd_val(pmd)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define pmd_present(pmd) (pmd_val(pmd) != 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define pmd_page_vaddr(pmd) ((unsigned long) __va(pmd_val(pmd) & _PFN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define pmd_page(pmd) virt_to_page((pmd_val(pmd) + PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define pud_none(pud) (!pud_val(pud))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define pud_bad(pud) (!ia64_phys_addr_valid(pud_val(pud)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define pud_present(pud) (pud_val(pud) != 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define pud_page_vaddr(pud) ((unsigned long) __va(pud_val(pud) & _PFN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define pud_page(pud) virt_to_page((pud_val(pud) + PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #if CONFIG_PGTABLE_LEVELS == 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define p4d_none(p4d) (!p4d_val(p4d))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define p4d_bad(p4d) (!ia64_phys_addr_valid(p4d_val(p4d)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define p4d_present(p4d) (p4d_val(p4d) != 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define p4d_clear(p4dp) (p4d_val(*(p4dp)) = 0UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define p4d_page_vaddr(p4d) ((unsigned long) __va(p4d_val(p4d) & _PFN_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define p4d_page(p4d) virt_to_page((p4d_val(p4d) + PAGE_OFFSET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * The following have defined behavior only work if pte_present() is true.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define pte_write(pte) ((unsigned) (((pte_val(pte) & _PAGE_AR_MASK) >> _PAGE_AR_SHIFT) - 2) <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define pte_exec(pte) ((pte_val(pte) & _PAGE_AR_RX) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define pte_dirty(pte) ((pte_val(pte) & _PAGE_D) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define pte_young(pte) ((pte_val(pte) & _PAGE_A) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * Note: we convert AR_RWX to AR_RX and AR_RW to AR_R by clearing the 2nd bit in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * access rights:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define pte_wrprotect(pte) (__pte(pte_val(pte) & ~_PAGE_AR_RW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define pte_mkwrite(pte) (__pte(pte_val(pte) | _PAGE_AR_RW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define pte_mkold(pte) (__pte(pte_val(pte) & ~_PAGE_A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define pte_mkyoung(pte) (__pte(pte_val(pte) | _PAGE_A))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define pte_mkclean(pte) (__pte(pte_val(pte) & ~_PAGE_D))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define pte_mkdirty(pte) (__pte(pte_val(pte) | _PAGE_D))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define pte_mkhuge(pte) (__pte(pte_val(pte)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Because ia64's Icache and Dcache is not coherent (on a cpu), we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * sync icache and dcache when we insert *new* executable page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * __ia64_sync_icache_dcache() check Pg_arch_1 bit and flush icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * set_pte() is also called by the kernel, but we can expect that the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * flushes icache explicitly if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define pte_present_exec_user(pte)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ((pte_val(pte) & (_PAGE_P | _PAGE_PL_MASK | _PAGE_AR_RX)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) (_PAGE_P | _PAGE_PL_3 | _PAGE_AR_RX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) extern void __ia64_sync_icache_dcache(pte_t pteval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static inline void set_pte(pte_t *ptep, pte_t pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* page is present && page is user && page is executable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * && (page swapin or new page or page migraton
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * || copy_on_write with page copying.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (pte_present_exec_user(pteval) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) (!pte_present(*ptep) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) pte_pfn(*ptep) != pte_pfn(pteval)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* load_module() calles flush_icache_range() explicitly*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) __ia64_sync_icache_dcache(pteval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) *ptep = pteval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Make page protection values cacheable, uncacheable, or write-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * combining. Note that "protection" is really a misnomer here as the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * protection value contains the memory attribute bits, dirty bits, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * various other bits as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define pgprot_cacheable(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define pgprot_noncached(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_UC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define pgprot_writecombine(prot) __pgprot((pgprot_val(prot) & ~_PAGE_MA_MASK) | _PAGE_MA_WC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) unsigned long size, pgprot_t vma_prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define __HAVE_PHYS_MEM_ACCESS_PROT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) pgd_index (unsigned long address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) unsigned long region = address >> 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned long l1index = (address >> PGDIR_SHIFT) & ((PTRS_PER_PGD >> 3) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return (region << (PAGE_SHIFT - 6)) | l1index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define pgd_index pgd_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * In the kernel's mapped region we know everything is in region number 5, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * as an optimisation its PGD already points to the area for that region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * However, this also means that we cannot use pgd_index() and we must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * never add the region here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define pgd_offset_k(addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) (init_mm.pgd + (((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* Look up a pgd entry in the gate area. On IA-64, the gate-area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) resides in the kernel-mapped segment, hence we use pgd_offset_k()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define pgd_offset_gate(mm, addr) pgd_offset_k(addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* atomic versions of the some PTE manipulations: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ptep_test_and_clear_young (struct vm_area_struct *vma, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!pte_young(*ptep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return test_and_clear_bit(_PAGE_A_BIT, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) pte_t pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (!pte_young(pte))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) set_pte_at(vma->vm_mm, addr, ptep, pte_mkold(pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static inline pte_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return __pte(xchg((long *) ptep, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pte_t pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pte_clear(mm, addr, ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned long new, old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) old = pte_val(*ptep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) new = pte_val(pte_wrprotect(__pte (old)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } while (cmpxchg((unsigned long *) ptep, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) pte_t old_pte = *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) set_pte_at(mm, addr, ptep, pte_wrprotect(old_pte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pte_same (pte_t a, pte_t b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return pte_val(a) == pte_val(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define update_mmu_cache(vma, address, ptep) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) extern void paging_init (void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * Note: The macros below rely on the fact that MAX_SWAPFILES_SHIFT <= number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * bits in the swap-type field of the swap pte. It would be nice to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * enforce that, but we can't easily include <linux/swap.h> here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * (Of course, better still would be to define MAX_SWAPFILES_SHIFT here...).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Format of swap pte:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * bit 0 : present bit (must be zero)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * bits 1- 7: swap-type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * bits 8-62: swap offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * bit 63 : _PAGE_PROTNONE bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define __swp_type(entry) (((entry).val >> 1) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define __swp_offset(entry) (((entry).val << 1) >> 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 1) | ((long) (offset) << 8) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * ZERO_PAGE is a global shared page that is always zero: used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * for zero-mapped memory areas etc..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) extern struct page *zero_page_memmap_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define ZERO_PAGE(vaddr) (zero_page_memmap_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* We provide our own get_unmapped_area to cope with VA holes for userland */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define HAVE_ARCH_UNMAPPED_AREA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #ifdef CONFIG_HUGETLB_PAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define HUGETLB_PGDIR_SHIFT (HPAGE_SHIFT + 2*(PAGE_SHIFT-3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define HUGETLB_PGDIR_SIZE (__IA64_UL(1) << HUGETLB_PGDIR_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define HUGETLB_PGDIR_MASK (~(HUGETLB_PGDIR_SIZE-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * Update PTEP with ENTRY, which is guaranteed to be a less
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * restrictive PTE. That is, ENTRY may have the ACCESSED, DIRTY, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * WRITABLE bits turned on, when the value at PTEP did not. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * WRITABLE bit may only be turned if SAFELY_WRITABLE is TRUE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * SAFELY_WRITABLE is TRUE if we can update the value at PTEP without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * having to worry about races. On SMP machines, there are only two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * cases where this is true:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) * (1) *PTEP has the PRESENT bit turned OFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * (2) ENTRY has the DIRTY bit turned ON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * On ia64, we could implement this routine with a cmpxchg()-loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * which ORs in the _PAGE_A/_PAGE_D bit if they're set in ENTRY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * However, like on x86, we can get a more streamlined version by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) * observing that it is OK to drop ACCESSED bit updates when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) * SAFELY_WRITABLE is FALSE. Besides being rare, all that would do is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * result in an extra Access-bit fault, which would then turn on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * ACCESSED bit in the low-level fault handler (iaccess_bit or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * daccess_bit in ivt.S).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int __changed = !pte_same(*(__ptep), __entry); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (__changed && __safely_writable) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) set_pte(__ptep, __entry); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) flush_tlb_page(__vma, __addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __changed; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) # define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __safely_writable) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int __changed = !pte_same(*(__ptep), __entry); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (__changed) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) set_pte_at((__vma)->vm_mm, (__addr), __ptep, __entry); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) flush_tlb_page(__vma, __addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) __changed; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) # ifdef CONFIG_VIRTUAL_MEM_MAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* arch mem_map init routine is needed due to holes in a virtual mem_map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) void memmap_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) void arch_memmap_init(unsigned long size, int nid, unsigned long zone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) unsigned long start_pfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) # endif /* CONFIG_VIRTUAL_MEM_MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) # endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Identity-mapped regions use a large page size. We'll call such large pages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * "granules". If you can think of a better name that's unambiguous, let me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * know...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #if defined(CONFIG_IA64_GRANULE_64MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) # define IA64_GRANULE_SHIFT _PAGE_SIZE_64M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #elif defined(CONFIG_IA64_GRANULE_16MB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) # define IA64_GRANULE_SHIFT _PAGE_SIZE_16M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IA64_GRANULE_SIZE (1 << IA64_GRANULE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * log2() of the page size we use to map the kernel image (IA64_TR_KERNEL):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define KERNEL_TR_PAGE_SHIFT _PAGE_SIZE_64M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define KERNEL_TR_PAGE_SIZE (1 << KERNEL_TR_PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* These tell get_user_pages() that the first gate page is accessible from user-level. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define FIXADDR_USER_START GATE_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #ifdef HAVE_BUGGY_SEGREL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) # define FIXADDR_USER_END (GATE_ADDR + 2*PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) # define FIXADDR_USER_END (GATE_ADDR + 2*PERCPU_PAGE_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define __HAVE_ARCH_PTEP_SET_WRPROTECT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define __HAVE_ARCH_PTE_SAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define __HAVE_ARCH_PGD_OFFSET_GATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #if CONFIG_PGTABLE_LEVELS == 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #include <asm-generic/pgtable-nopud.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #include <asm-generic/pgtable-nop4d.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif /* _ASM_IA64_PGTABLE_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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