Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_IA64_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_IA64_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) struct pci_vector_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	__u16 segment;	/* PCI Segment number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	__u16 bus;	/* PCI Bus number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	__u32 pci_id;	/* ACPI split 16 bits device, 16 bits function (see section 6.1.1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	__u8 pin;	/* PCI PIN (0 = A, 1 = B, 2 = C, 3 = D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	__u32 irq;	/* IRQ assigned */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)  * Can be used to override the logic in pci_scan_bus for skipping already-configured bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  * numbers - to be used for buggy BIOSes or architectures with incomplete PCI setup by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)  * loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define pcibios_assign_all_busses()     0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PCIBIOS_MIN_IO		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PCIBIOS_MIN_MEM		0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HAVE_PCI_MMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ARCH_GENERIC_PCI_MMAP_RESOURCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define arch_can_pci_mmap_wc()	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HAVE_PCI_LEGACY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) extern int pci_mmap_legacy_page_range(struct pci_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 				      struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 				      enum pci_mmap_state mmap_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) char *pci_get_legacy_mem(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct pci_controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	struct acpi_device *companion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	void *iommu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	int segment;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	int node;		/* nearest node with memory or NUMA_NO_NODE for global allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	void *platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCI_CONTROLLER(busdev) ((struct pci_controller *) busdev->sysdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define pci_domain_nr(busdev)    (PCI_CONTROLLER(busdev)->segment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) extern struct pci_ops pci_root_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static inline int pci_proc_domain(struct pci_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	return (pci_domain_nr(bus) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	return channel ? isa_irq_to_vector(15) : isa_irq_to_vector(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #endif /* _ASM_IA64_PCI_H */