^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_IA64_PAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_IA64_PAL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Processor Abstraction Layer definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * chapter 11 IA-64 Processor Abstraction Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1998-2001 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Stephane Eranian <eranian@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1999 VA Linux Systems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2008 Silicon Graphics, Inc. (SGI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * 99/10/01 davidm Make sure we pass zero for reserved parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * 00/05/25 eranian Support for stack calls, and static physical calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 00/06/18 eranian Support for stacked physical calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 06/10/26 rja Support for Intel Itanium Architecture Software Developer's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Manual Rev 2.2 (Jan 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Note that some of these calls use a static-register only calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * convention which has nothing to do with the regular calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * convention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PAL_CACHE_FLUSH 1 /* flush i/d cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PAL_CACHE_INIT 3 /* initialize i/d cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PAL_CACHE_SUMMARY 4 /* get summary of cache hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PAL_PTCE_INFO 6 /* purge TLB info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PAL_VM_INFO 7 /* return supported virtual memory features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PAL_DEBUG_INFO 11 /* get number of debug registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PAL_FREQ_BASE 13 /* base frequency of the platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PAL_PERF_MON_INFO 15 /* return performance monitor info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PAL_RSE_INFO 19 /* return rse information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PAL_VERSION 20 /* return version of PAL code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PAL_MC_RESUME 26 /* Return to interrupted process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PAL_HALT 28 /* enter the low power HALT state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PAL_CACHE_SHARED_INFO 43 /* returns information on caches shared by logical processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PAL_GET_HW_POLICY 48 /* Get current hardware resource sharing policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PAL_SET_HW_POLICY 49 /* Set current hardware resource sharing policy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PAL_VP_INFO 50 /* Information about virtual processor features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PAL_MC_HW_TRACKING 51 /* Hardware tracking status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PAL_TEST_PROC 258 /* perform late processor self-test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PAL_VM_TR_READ 261 /* read contents of translation register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PAL_GET_PSTATE 262 /* get the current P-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PAL_SET_PSTATE 263 /* set the P-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PAL_BRAND_INFO 274 /* Processor branding information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PAL_GET_PSTATE_TYPE_LASTSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PAL_GET_PSTATE_TYPE_AVGANDRESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PAL_GET_PSTATE_TYPE_AVGNORESET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PAL_GET_PSTATE_TYPE_INSTANT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PAL_MC_ERROR_INJECT 276 /* Injects processor error or returns injection capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #include <asm/fpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Data types needed to pass information into PAL procedures and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * interpret information returned by them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Return status from the PAL procedure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) typedef s64 pal_status_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PAL_STATUS_SUCCESS 0 /* No error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PAL_STATUS_ERROR (-3) /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * specified level and type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * cache without sideeffects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * and "restrict" was 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PAL_STATUS_REQUIRES_MEMORY (-9) /* Call requires PAL memory buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Processor cache level in the hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) typedef u64 pal_cache_level_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PAL_CACHE_LEVEL_L0 0 /* L0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PAL_CACHE_LEVEL_L1 1 /* L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PAL_CACHE_LEVEL_L2 2 /* L2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Processor cache type at a particular level in the hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) typedef u64 pal_cache_type_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Processor cache line size in bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) typedef int pal_cache_line_size_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Processor cache line state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) typedef u64 pal_cache_line_state_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) typedef struct pal_freq_ratio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 den, num; /* numerator & denominator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) } itc_ratio, proc_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) typedef union pal_cache_config_info_1_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u64 u : 1, /* 0 Unified cache ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) at : 2, /* 2-1 Cache mem attr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) reserved : 5, /* 7-3 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) associativity : 8, /* 16-8 Associativity*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) line_size : 8, /* 23-17 Line size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) stride : 8, /* 31-24 Stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) store_latency : 8, /*39-32 Store latency*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) load_latency : 8, /* 47-40 Load latency*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) store_hints : 8, /* 55-48 Store hints*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) load_hints : 8; /* 63-56 Load hints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } pcci1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u64 pcci1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) } pal_cache_config_info_1_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) typedef union pal_cache_config_info_2_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 cache_size; /*cache size in bytes*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 alias_boundary : 8, /* 39-32 aliased addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * separation for max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) tag_ls_bit : 8, /* 47-40 LSb of addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) tag_ms_bit : 8, /* 55-48 MSb of addr*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) reserved : 8; /* 63-56 Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) } pcci2_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u64 pcci2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) } pal_cache_config_info_2_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) typedef struct pal_cache_config_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pal_status_t pcci_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) pal_cache_config_info_1_t pcci_info_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) pal_cache_config_info_2_t pcci_info_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u64 pcci_reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) } pal_cache_config_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define pcci_stride pcci_info_1.pcci1_bits.stride
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define pcci_line_size pcci_info_1.pcci1_bits.line_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define pcci_assoc pcci_info_1.pcci1_bits.associativity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define pcci_cache_attr pcci_info_1.pcci1_bits.at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define pcci_unified pcci_info_1.pcci1_bits.u
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* Possible values for cache attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PAL_CACHE_ATTR_WT 0 /* Write through cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PAL_CACHE_ATTR_WB 1 /* Write back cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * back depending on TLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * memory attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Possible values for cache hints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* Processor cache protection information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) typedef union pal_cache_protection_element_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 pcpi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 data_bits : 8, /* # data bits covered by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * each unit of protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) tagprot_lsb : 6, /* Least -do- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) tagprot_msb : 6, /* Most Sig. tag address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * bit that this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * protection covers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) prot_bits : 6, /* # of protection bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) method : 4, /* Protection method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) t_d : 2; /* Indicates which part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * of the cache this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * protection encoding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * applies.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } pcp_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) } pal_cache_protection_element_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define pcpi_cache_prot_part pcp_info.t_d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define pcpi_prot_method pcp_info.method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define pcpi_prot_bits pcp_info.prot_bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define pcpi_tagprot_msb pcp_info.tagprot_msb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define pcpi_data_bits pcp_info.data_bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Processor cache part encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * more significant )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * more significant )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define PAL_CACHE_PROT_PART_MAX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) typedef struct pal_cache_protection_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) pal_status_t pcpi_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) } pal_cache_protection_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Processor cache protection method encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Processor cache line identification in the hierarchy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) typedef union pal_cache_line_id_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u64 pclid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u64 cache_type : 8, /* 7-0 cache type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) level : 8, /* 15-8 level of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * cache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * hierarchy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) way : 8, /* 23-16 way in the set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) part : 8, /* 31-24 part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) reserved : 32; /* 63-32 is reserved*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) } pclid_info_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u64 cache_type : 8, /* 7-0 cache type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) level : 8, /* 15-8 level of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * cache in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * hierarchy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) way : 8, /* 23-16 way in the set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) part : 8, /* 31-24 part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mesi : 8, /* 39-32 cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) start : 8, /* 47-40 lsb of data to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * invert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) length : 8, /* 55-48 #bits to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * invert
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) trigger : 8; /* 63-56 Trigger error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * by doing a load
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * after the write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) } pclid_info_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } pal_cache_line_id_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define pclid_read_part pclid_info_read.part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define pclid_read_way pclid_info_read.way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define pclid_read_level pclid_info_read.level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define pclid_read_cache_type pclid_info_read.cache_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define pclid_write_trigger pclid_info_write.trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define pclid_write_length pclid_info_write.length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define pclid_write_start pclid_info_write.start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define pclid_write_mesi pclid_info_write.mesi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define pclid_write_part pclid_info_write.part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define pclid_write_way pclid_info_write.way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define pclid_write_level pclid_info_write.level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define pclid_write_cache_type pclid_info_write.cache_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Processor cache line part encodings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) typedef struct pal_cache_line_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pal_status_t pcli_status; /* Return status of the read cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * info call.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u64 pcli_data; /* 64-bit data, tag, protection bits .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u64 pcli_data_len; /* data length in bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } pal_cache_line_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Machine Check related crap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Pending event status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) typedef u64 pal_mc_pending_events_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define PAL_MC_PENDING_MCA (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define PAL_MC_PENDING_INIT (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* Error information type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) typedef u64 pal_mc_info_index_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define PAL_TLB_CHECK_OP_PURGE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) typedef struct pal_process_state_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u64 reserved1 : 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rz : 1, /* PAL_CHECK processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * rendezvous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ra : 1, /* PAL_CHECK attempted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * a rendezvous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) me : 1, /* Distinct multiple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * errors occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mn : 1, /* Min. state save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) * area has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * registered with PAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) sy : 1, /* Storage integrity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * synched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) co : 1, /* Continuable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ci : 1, /* MC isolated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) us : 1, /* Uncontained storage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * damage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) hd : 1, /* Non-essential hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * lost (no loss of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * functionality)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * causing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * processor to run in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * degraded mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) tl : 1, /* 1 => MC occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * after an instr was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * executed but before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * the trap that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * resulted from instr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * execution was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * generated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * (Trap Lost )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mi : 1, /* More information available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * call PAL_MC_ERROR_INFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) pi : 1, /* Precise instruction pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) pm : 1, /* Precise min-state save area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dy : 1, /* Processor dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * state valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) in : 1, /* 0 = MC, 1 = INIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) rs : 1, /* RSE valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cm : 1, /* MC corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ex : 1, /* MC is expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) cr : 1, /* Control regs valid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) pc : 1, /* Perf cntrs valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dr : 1, /* Debug regs valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) tr : 1, /* Translation regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) rr : 1, /* Region regs valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ar : 1, /* App regs valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) br : 1, /* Branch regs valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) pr : 1, /* Predicate registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) fp : 1, /* fp registers valid*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) b1 : 1, /* Preserved bank one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * general registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) b0 : 1, /* Preserved bank zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * general registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) gr : 1, /* General registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * are valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * (excl. banked regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dsize : 16, /* size of dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * state returned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * by the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) se : 1, /* Shared error. MCA in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) shared structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) reserved2 : 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) cc : 1, /* Cache check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) tc : 1, /* TLB check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bc : 1, /* Bus check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) rc : 1, /* Register file check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) uc : 1; /* Uarch check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) } pal_processor_state_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) typedef struct pal_cache_check_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u64 op : 4, /* Type of cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * operation that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * caused the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) level : 2, /* Cache level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) reserved1 : 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) dl : 1, /* Failure in data part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * of cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) tl : 1, /* Failure in tag part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * of cache line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dc : 1, /* Failure in dcache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ic : 1, /* Failure in icache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mesi : 3, /* Cache line state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) mv : 1, /* mesi valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) way : 5, /* Way in which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) wiv : 1, /* Way field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) reserved2 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dp : 1, /* Data poisoned on MBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) reserved3 : 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) hlth : 2, /* Health indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) index : 20, /* Cache line index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reserved4 : 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) is : 1, /* instruction set (1 == ia32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) iv : 1, /* instruction set field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pl : 2, /* privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) pv : 1, /* privilege level field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mcc : 1, /* Machine check corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) tv : 1, /* Target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rq : 1, /* Requester identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rp : 1, /* Responder identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) pi : 1; /* Precise instruction pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) } pal_cache_check_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) typedef struct pal_tlb_check_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u64 tr_slot : 8, /* Slot# of TR where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) trv : 1, /* tr_slot field is valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) reserved1 : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) level : 2, /* TLB level where failure occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) reserved2 : 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dtr : 1, /* Fail in data TR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) itr : 1, /* Fail in inst TR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dtc : 1, /* Fail in data TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) itc : 1, /* Fail in inst. TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) op : 4, /* Cache operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) reserved3 : 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) hlth : 2, /* Health indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) reserved4 : 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) is : 1, /* instruction set (1 == ia32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) iv : 1, /* instruction set field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pl : 2, /* privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) pv : 1, /* privilege level field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mcc : 1, /* Machine check corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) tv : 1, /* Target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) rq : 1, /* Requester identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) rp : 1, /* Responder identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pi : 1; /* Precise instruction pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) } pal_tlb_check_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) typedef struct pal_bus_check_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) u64 size : 5, /* Xaction size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ib : 1, /* Internal bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) eb : 1, /* External bus error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) cc : 1, /* Error occurred
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * during cache-cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) type : 8, /* Bus xaction type*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) sev : 5, /* Bus error severity*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) hier : 2, /* Bus hierarchy level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dp : 1, /* Data poisoned on MBE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bsi : 8, /* Bus error status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) * info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) reserved2 : 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) is : 1, /* instruction set (1 == ia32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) iv : 1, /* instruction set field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) pl : 2, /* privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) pv : 1, /* privilege level field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mcc : 1, /* Machine check corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) tv : 1, /* Target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) rq : 1, /* Requester identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) rp : 1, /* Responder identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pi : 1; /* Precise instruction pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } pal_bus_check_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) typedef struct pal_reg_file_check_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u64 id : 4, /* Register file identifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) op : 4, /* Type of register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * operation that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * caused the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) reg_num : 7, /* Register number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) rnv : 1, /* reg_num valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) reserved2 : 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) is : 1, /* instruction set (1 == ia32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) iv : 1, /* instruction set field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) pl : 2, /* privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) pv : 1, /* privilege level field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) mcc : 1, /* Machine check corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reserved3 : 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pi : 1; /* Precise instruction pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) } pal_reg_file_check_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) typedef struct pal_uarch_check_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) u64 sid : 5, /* Structure identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) level : 3, /* Level of failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) array_id : 4, /* Array identification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) op : 4, /* Type of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * operation that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * caused the machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * check.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) way : 6, /* Way of structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) wv : 1, /* way valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) xv : 1, /* index valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) reserved1 : 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) hlth : 2, /* Health indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) index : 8, /* Index or set of the uarch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * structure that failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) reserved2 : 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) is : 1, /* instruction set (1 == ia32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) iv : 1, /* instruction set field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pl : 2, /* privilege level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) pv : 1, /* privilege level field valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mcc : 1, /* Machine check corrected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) tv : 1, /* Target address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) rq : 1, /* Requester identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) rp : 1, /* Responder identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pi : 1; /* Precise instruction pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * structure is valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } pal_uarch_check_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) typedef union pal_mc_error_info_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u64 pmei_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pal_processor_state_info_t pme_processor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) pal_cache_check_info_t pme_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pal_tlb_check_info_t pme_tlb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pal_bus_check_info_t pme_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) pal_reg_file_check_info_t pme_reg_file;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) pal_uarch_check_info_t pme_uarch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } pal_mc_error_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define pmci_proc_unknown_check pme_processor.uc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define pmci_proc_bus_check pme_processor.bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define pmci_proc_tlb_check pme_processor.tc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define pmci_proc_cache_check pme_processor.cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define pmci_proc_dynamic_state_size pme_processor.dsize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define pmci_proc_gpr_valid pme_processor.gr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define pmci_proc_fp_valid pme_processor.fp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define pmci_proc_predicate_regs_valid pme_processor.pr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #define pmci_proc_branch_regs_valid pme_processor.br
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define pmci_proc_app_regs_valid pme_processor.ar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define pmci_proc_region_regs_valid pme_processor.rr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define pmci_proc_translation_regs_valid pme_processor.tr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define pmci_proc_debug_regs_valid pme_processor.dr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define pmci_proc_perf_counters_valid pme_processor.pc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define pmci_proc_control_regs_valid pme_processor.cr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define pmci_proc_machine_check_expected pme_processor.ex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define pmci_proc_machine_check_corrected pme_processor.cm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define pmci_proc_rse_valid pme_processor.rs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define pmci_proc_machine_check_or_init pme_processor.in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define pmci_proc_dynamic_state_valid pme_processor.dy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define pmci_proc_operation pme_processor.op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define pmci_proc_trap_lost pme_processor.tl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define pmci_proc_hardware_damage pme_processor.hd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define pmci_proc_uncontained_storage_damage pme_processor.us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define pmci_proc_machine_check_isolated pme_processor.ci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define pmci_proc_continuable pme_processor.co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define pmci_proc_storage_intergrity_synced pme_processor.sy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define pmci_proc_min_state_save_area_regd pme_processor.mn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define pmci_proc_distinct_multiple_errors pme_processor.me
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define pmci_proc_pal_rendezvous_complete pme_processor.rz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define pmci_cache_level pme_cache.level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define pmci_cache_line_state pme_cache.mesi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define pmci_cache_line_state_valid pme_cache.mv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define pmci_cache_line_index pme_cache.index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define pmci_cache_instr_cache_fail pme_cache.ic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define pmci_cache_data_cache_fail pme_cache.dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define pmci_cache_line_tag_fail pme_cache.tl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define pmci_cache_line_data_fail pme_cache.dl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define pmci_cache_operation pme_cache.op
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define pmci_cache_way_valid pme_cache.wv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define pmci_cache_target_address_valid pme_cache.tv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define pmci_cache_way pme_cache.way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define pmci_cache_mc pme_cache.mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define pmci_tlb_mc pme_tlb.mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define pmci_bus_status_info pme_bus.bsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define pmci_bus_req_address_valid pme_bus.rq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define pmci_bus_resp_address_valid pme_bus.rp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define pmci_bus_target_address_valid pme_bus.tv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define pmci_bus_error_severity pme_bus.sev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define pmci_bus_transaction_type pme_bus.type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define pmci_bus_cache_cache_transfer pme_bus.cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define pmci_bus_transaction_size pme_bus.size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define pmci_bus_internal_error pme_bus.ib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #define pmci_bus_external_error pme_bus.eb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define pmci_bus_mc pme_bus.mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * NOTE: this min_state_save area struct only includes the 1KB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * architectural state save area. The other 3 KB is scratch space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * for PAL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) typedef struct pal_min_state_area_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u64 pmsa_nat_bits; /* nat bits for saved GRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u64 pmsa_gr[15]; /* GR1 - GR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) u64 pmsa_pr; /* predicate registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u64 pmsa_br0; /* branch register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u64 pmsa_rsc; /* ar.rsc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u64 pmsa_iip; /* cr.iip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u64 pmsa_ipsr; /* cr.ipsr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u64 pmsa_ifs; /* cr.ifs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u64 pmsa_xip; /* previous iip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u64 pmsa_xpsr; /* previous psr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u64 pmsa_xfs; /* previous ifs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u64 pmsa_br1; /* branch register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } pal_min_state_area_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct ia64_pal_retval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * A zero status value indicates call completed without error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * A negative status value indicates reason of call failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * A positive status value indicates success but an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * informational value should be printed (e.g., "reboot for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * change to take effect").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) s64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u64 v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u64 v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u64 v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * Note: Currently unused PAL arguments are generally labeled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * "reserved" so the value specified in the PAL documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * (generally 0) MUST be passed. Reserved parameters are not optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * parameters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct ia64_fpreg fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ia64_save_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) iprv = ia64_pal_call_static(a0, a1, a2, a3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ia64_load_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct ia64_fpreg fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ia64_save_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ia64_load_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct ia64_fpreg fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ia64_save_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ia64_load_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ia64_fpreg fr[6]; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ia64_save_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ia64_load_scratch_fpregs(fr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) typedef int (*ia64_pal_handler) (u64, ...);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) extern ia64_pal_handler ia64_pal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) extern void ia64_pal_handler_init (void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) extern ia64_pal_handler ia64_pal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) extern pal_cache_config_info_t l0d_cache_config_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) extern pal_cache_config_info_t l0i_cache_config_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) extern pal_cache_config_info_t l1_cache_config_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) extern pal_cache_config_info_t l2_cache_config_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) extern pal_cache_protection_info_t l0d_cache_protection_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) extern pal_cache_protection_info_t l0i_cache_protection_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) extern pal_cache_protection_info_t l1_cache_protection_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) extern pal_cache_protection_info_t l2_cache_protection_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) pal_cache_type_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pal_cache_type_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) extern void pal_error(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Useful wrappers for the current list of pal procedures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) typedef union pal_bus_features_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u64 pal_bus_features_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u64 pbf_reserved1 : 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) u64 pbf_req_bus_parking : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u64 pbf_bus_lock_mask : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u64 pbf_enable_half_xfer_rate : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) u64 pbf_reserved2 : 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u64 pbf_enable_shared_line_replace : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u64 pbf_enable_exclusive_line_replace : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u64 pbf_disable_xaction_queueing : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u64 pbf_disable_resp_err_check : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u64 pbf_disable_berr_check : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) u64 pbf_disable_bus_req_internal_err_signal : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u64 pbf_disable_bus_req_berr_signal : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u64 pbf_disable_bus_init_event_check : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u64 pbf_disable_bus_init_event_signal : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u64 pbf_disable_bus_addr_err_check : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u64 pbf_disable_bus_addr_err_signal : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u64 pbf_disable_bus_data_err_check : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) } pal_bus_features_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } pal_bus_features_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) extern void pal_bus_features_print (u64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Provide information about configurable processor bus features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pal_bus_features_u_t *features_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pal_bus_features_u_t *features_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (features_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) features_avail->pal_bus_features_val = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (features_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) features_status->pal_bus_features_val = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (features_control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) features_control->pal_bus_features_val = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Enables/disables specific processor bus features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Get detailed cache information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (iprv.status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) conf->pcci_status = iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) conf->pcci_info_1.pcci1_data = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) conf->pcci_info_2.pcci2_data = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) conf->pcci_reserved = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Get detailed cche protection information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (iprv.status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) prot->pcpi_status = iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * Flush the processor instruction or data caches. *PROGRESS must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * initialized to zero before calling this for the first time..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PAL_CALL(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *vector = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) *progress = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Initialize the processor controlled caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* Initialize the tags and data of a data or unified cache line of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * processor controlled cache to known values without the availability
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * of backing memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* Read the data and tag of a processor controlled cache line for diags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PAL_CALL_PHYS_STK(iprv, PAL_CACHE_READ, line_id.pclid_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) physical_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* Return summary information about the hierarchy of caches controlled by the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static inline long ia64_pal_cache_summary(unsigned long *cache_levels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned long *unique_caches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (cache_levels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) *cache_levels = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (unique_caches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) *unique_caches = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Write the data and tag of a processor-controlled cache line for diags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PAL_CALL_PHYS_STK(iprv, PAL_CACHE_WRITE, line_id.pclid_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) physical_addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) u64 *buffer_size, u64 *buffer_align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (buffer_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *buffer_size = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (buffer_align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) *buffer_align = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Copy relocatable PAL procedures from ROM to memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (pal_proc_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) *pal_proc_offset = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Return the number of instruction and data debug register pairs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static inline long ia64_pal_debug_info(unsigned long *inst_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned long *data_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (inst_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) *inst_regs = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (data_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) *data_regs = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #ifdef TBD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Switch from IA64-system environment to IA-32 system environment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) /* Get unique geographical address of this processor on its bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ia64_pal_fixed_addr (u64 *global_unique_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (global_unique_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) *global_unique_addr = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Get base frequency of the platform if generated by the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static inline long ia64_pal_freq_base(unsigned long *platform_base_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (platform_base_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) *platform_base_freq = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * Get the ratios for processor frequency, bus frequency and interval timer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * to base frequency of the platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct pal_freq_ratio *itc_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (proc_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) *(u64 *)proc_ratio = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (bus_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) *(u64 *)bus_ratio = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (itc_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) *(u64 *)itc_ratio = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * Get the current hardware resource sharing policy of the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ia64_pal_get_hw_policy (u64 proc_num, u64 *cur_policy, u64 *num_impacted,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u64 *la)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PAL_CALL(iprv, PAL_GET_HW_POLICY, proc_num, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (cur_policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *cur_policy = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (num_impacted)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) *num_impacted = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (la)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) *la = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Make the processor enter HALT or one of the implementation dependent low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * power states where prefetching and execution are suspended and cache and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * TLB coherency is not maintained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ia64_pal_halt (u64 halt_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) typedef union pal_power_mgmt_info_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u64 ppmi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u64 exit_latency : 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) entry_latency : 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) power_consumption : 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) im : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) co : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) reserved : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } pal_power_mgmt_info_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) } pal_power_mgmt_info_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Return information about processor's optional power management capabilities. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Get the current P-state information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) ia64_pal_get_pstate (u64 *pstate_index, unsigned long type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PAL_CALL_STK(iprv, PAL_GET_PSTATE, type, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) *pstate_index = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* Set the P-state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ia64_pal_set_pstate (u64 pstate_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Processor branding information*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ia64_pal_get_brand_info (char *brand_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PAL_CALL_STK(iprv, PAL_BRAND_INFO, 0, (u64)brand_info, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * suspended, but cache and TLB coherency is maintained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ia64_pal_halt_light (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Clear all the processor error logging registers and reset the indicator that allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * the error logging registers to be written. This procedure also checks the pending
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) * machine check bit and pending INIT bit and reports their states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ia64_pal_mc_clear_log (u64 *pending_vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (pending_vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) *pending_vector = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* Ensure that all outstanding transactions in a processor are completed or that any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * MCA due to thes outstanding transaction is taken.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ia64_pal_mc_drain (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Return the machine check dynamic processor state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ia64_pal_mc_dynamic_state (u64 info_type, u64 dy_buffer, u64 *size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, info_type, dy_buffer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) *size = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* Return processor machine check information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) *size = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (error_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) *error_info = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Injects the requested processor error or returns info on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * supported injection capabilities for current processor implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u64 err_data_buffer, u64 *capabilities, u64 *resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) err_struct_info, err_data_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (capabilities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) *capabilities= iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) *resources= iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) u64 err_data_buffer, u64 *capabilities, u64 *resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) err_struct_info, err_data_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (capabilities)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) *capabilities= iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (resources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) *resources= iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) * attempt to correct any expected machine checks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ia64_pal_mc_expected (u64 expected, u64 *previous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (previous)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) *previous = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) typedef union pal_hw_tracking_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u64 pht_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) u64 itc :4, /* Instruction cache tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dct :4, /* Date cache tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) itt :4, /* Instruction TLB tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ddt :4, /* Data TLB tracking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) reserved:48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) } pal_hw_tracking_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) } pal_hw_tracking_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * Hardware tracking status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ia64_pal_mc_hw_tracking (u64 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PAL_CALL(iprv, PAL_MC_HW_TRACKING, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) *status = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* Register a platform dependent location with PAL to which it can save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * minimal processor state in the event of a machine check or initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) * event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ia64_pal_mc_register_mem (u64 physical_addr, u64 size, u64 *req_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, size, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (req_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) *req_size = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* Restore minimal architectural processor state, set CMC interrupt if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * and resume execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) /* Return the memory attributes implemented by the processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ia64_pal_mem_attrib (u64 *mem_attrib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (mem_attrib)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) *mem_attrib = iprv.v0 & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) /* Return the amount of memory needed for second phase of processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) * self-test and the required alignment of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (bytes_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) *bytes_needed = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (alignment)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) *alignment = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) typedef union pal_perf_mon_info_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) u64 ppmi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) u64 generic : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) width : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) cycles : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) retired : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) reserved : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) } pal_perf_mon_info_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) } pal_perf_mon_info_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Return the performance monitor information about what can be counted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * and how to configure the monitors to count the desired events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (pm_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pm_info->ppmi_data = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* Specifies the physical address of the processor interrupt block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * and I/O port space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ia64_pal_platform_addr (u64 type, u64 physical_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Set the SAL PMI entrypoint in memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) struct pal_features_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* Provide information about configurable processor features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) ia64_pal_proc_get_features (u64 *features_avail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u64 *features_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u64 *features_control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u64 features_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, features_set, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (iprv.status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) *features_avail = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) *features_status = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) *features_control = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Enable/disable processor dependent features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ia64_pal_proc_set_features (u64 feature_select)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) * Put everything in a struct so we avoid the global offset table whenever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) typedef struct ia64_ptce_info_s {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u32 count[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 stride[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) } ia64_ptce_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Return the information required for the architected loop used to purge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * (initialize) the entire TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ia64_get_ptce (ia64_ptce_info_t *ptce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (!ptce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (iprv.status == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ptce->base = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ptce->count[0] = iprv.v1 >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ptce->count[1] = iprv.v1 & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ptce->stride[0] = iprv.v2 >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ptce->stride[1] = iprv.v2 & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Return info about implemented application and control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) if (reg_info_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *reg_info_1 = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (reg_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) *reg_info_2 = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) typedef union pal_hints_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) unsigned long ph_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) unsigned long si : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) li : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) reserved : 62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) } pal_hints_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) } pal_hints_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Return information about the register stack and RSE for this processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static inline long ia64_pal_rse_info(unsigned long *num_phys_stacked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) pal_hints_u_t *hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (num_phys_stacked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) *num_phys_stacked = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (hints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) hints->ph_data = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * Set the current hardware resource sharing policy of the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ia64_pal_set_hw_policy (u64 policy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) PAL_CALL(iprv, PAL_SET_HW_POLICY, policy, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * suspended, but cause cache and TLB coherency to be maintained.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * This is usually called in IA-32 mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) ia64_pal_shutdown (void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* Perform the second phase of processor self-test. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (self_test_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) *self_test_state = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) typedef union pal_version_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) u64 pal_version_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) u64 pv_pal_b_rev : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u64 pv_pal_b_model : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) u64 pv_reserved1 : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u64 pv_pal_vendor : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u64 pv_pal_a_rev : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) u64 pv_pal_a_model : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) u64 pv_reserved2 : 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) } pal_version_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) } pal_version_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * Return PAL version information. While the documentation states that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) * PAL_VERSION can be called in either physical or virtual mode, some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) * implementations only allow physical calls. We don't call it very often,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) * so the overhead isn't worth eliminating.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (pal_min_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) pal_min_version->pal_version_val = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (pal_cur_version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) pal_cur_version->pal_version_val = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) typedef union pal_tc_info_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u64 pti_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) u64 num_sets : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) associativity : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) num_entries : 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) pf : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) unified : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) reduce_tr : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) reserved : 29;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) } pal_tc_info_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } pal_tc_info_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define tc_reduce_tr pal_tc_info_s.reduce_tr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define tc_unified pal_tc_info_s.unified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define tc_pf pal_tc_info_s.pf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define tc_num_entries pal_tc_info_s.num_entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) #define tc_associativity pal_tc_info_s.associativity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define tc_num_sets pal_tc_info_s.num_sets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* Return information about the virtual memory characteristics of the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) * implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (tc_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) tc_info->pti_val = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (tc_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) *tc_pages = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* Get page size information about the virtual memory characteristics of the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) * implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static inline s64 ia64_pal_vm_page_size(u64 *tr_pages, u64 *vw_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (tr_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) *tr_pages = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (vw_pages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) *vw_pages = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) typedef union pal_vm_info_1_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) u64 pvi1_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) u64 vw : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) phys_add_size : 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) key_size : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) max_pkr : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) hash_tag_id : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) max_dtr_entry : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) max_itr_entry : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) max_unique_tcs : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) num_tc_levels : 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) } pal_vm_info_1_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) } pal_vm_info_1_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define PAL_MAX_PURGES 0xFFFF /* all ones is means unlimited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) typedef union pal_vm_info_2_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) u64 pvi2_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) u64 impl_va_msb : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) rid_size : 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) max_purges : 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) reserved : 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) } pal_vm_info_2_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) } pal_vm_info_2_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* Get summary information about the virtual memory characteristics of the processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) * implementation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (vm_info_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) vm_info_1->pvi1_val = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (vm_info_2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) vm_info_2->pvi2_val = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) typedef union pal_vp_info_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) u64 pvi_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) u64 index: 48, /* virtual feature set info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) vmm_id: 16; /* feature set id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) } pal_vp_info_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) } pal_vp_info_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) * Returns information about virtual processor features
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) ia64_pal_vp_info (u64 feature_set, u64 vp_buffer, u64 *vp_info, u64 *vmm_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) PAL_CALL(iprv, PAL_VP_INFO, feature_set, vp_buffer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) if (vp_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) *vp_info = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (vmm_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) *vmm_id = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) typedef union pal_itr_valid_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u64 piv_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u64 access_rights_valid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) priv_level_valid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) dirty_bit_valid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) mem_attr_valid : 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) reserved : 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) } pal_tr_valid_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) } pal_tr_valid_u_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* Read a translation register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (tr_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) tr_valid->piv_val = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) * PAL_PREFETCH_VISIBILITY transaction types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) #define PAL_VISIBILITY_VIRTUAL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define PAL_VISIBILITY_PHYSICAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * PAL_PREFETCH_VISIBILITY return codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define PAL_VISIBILITY_OK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define PAL_VISIBILITY_INVAL_ARG -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define PAL_VISIBILITY_ERROR -3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ia64_pal_prefetch_visibility (s64 trans_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* data structure for getting information on logical to physical mappings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) typedef union pal_log_overview_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) u64 num_log :16, /* Total number of logical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) * processors on this die
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) tpc :8, /* Threads per core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) reserved3 :8, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) cpp :8, /* Cores per processor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) reserved2 :8, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) ppid :8, /* Physical processor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) reserved1 :8; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) } overview_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) u64 overview_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) } pal_log_overview_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) typedef union pal_proc_n_log_info1_u{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) u64 tid :16, /* Thread id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) reserved2 :16, /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) cid :16, /* Core id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) reserved1 :16; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) } ppli1_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) u64 ppli1_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) } pal_proc_n_log_info1_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) typedef union pal_proc_n_log_info2_u {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) u64 la :16, /* Logical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) reserved :48; /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) } ppli2_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) u64 ppli2_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) } pal_proc_n_log_info2_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) typedef struct pal_logical_to_physical_s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) pal_log_overview_t overview;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) pal_proc_n_log_info1_t ppli1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) pal_proc_n_log_info2_t ppli2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) } pal_logical_to_physical_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define overview_num_log overview.overview_bits.num_log
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define overview_tpc overview.overview_bits.tpc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define overview_cpp overview.overview_bits.cpp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define overview_ppid overview.overview_bits.ppid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define log1_tid ppli1.ppli1_bits.tid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define log1_cid ppli1.ppli1_bits.cid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define log2_la ppli2.ppli2_bits.la
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* Get information on logical to physical processor mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (iprv.status == PAL_STATUS_SUCCESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) mapping->overview.overview_data = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) mapping->ppli1.ppli1_data = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) mapping->ppli2.ppli2_data = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) typedef struct pal_cache_shared_info_s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) u64 num_shared;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) pal_proc_n_log_info1_t ppli1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) pal_proc_n_log_info2_t ppli2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) } pal_cache_shared_info_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) /* Get information on logical to physical processor mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static inline s64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ia64_pal_cache_shared_info(u64 level,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) u64 type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) u64 proc_number,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) pal_cache_shared_info_t *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) struct ia64_pal_retval iprv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) PAL_CALL(iprv, PAL_CACHE_SHARED_INFO, level, type, proc_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (iprv.status == PAL_STATUS_SUCCESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) info->num_shared = iprv.v0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) info->ppli1.ppli1_data = iprv.v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) info->ppli2.ppli2_data = iprv.v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return iprv.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #endif /* __ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #endif /* _ASM_IA64_PAL_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags