^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_IA64_KREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_IA64_KREGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2001-2002 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file defines the kernel register usage convention used by Linux/ia64.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Kernel registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IA64_KR_IO_BASE 0 /* ar.k0: legacy I/O base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IA64_KR_TSSD 1 /* ar.k1: IVE uses this as the TSSD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IA64_KR_PER_CPU_DATA 3 /* ar.k3: physical per-CPU base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IA64_KR_CURRENT_STACK 4 /* ar.k4: what's mapped in IA64_TR_CURRENT_STACK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IA64_KR_FPU_OWNER 5 /* ar.k5: fpu-owner (UP only, at the moment) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IA64_KR_CURRENT 6 /* ar.k6: "current" task pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IA64_KR_PT_BASE 7 /* ar.k7: page table base address (physical) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define _IA64_KR_PASTE(x,y) x##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define _IA64_KR_PREFIX(n) _IA64_KR_PASTE(ar.k, n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IA64_KR(n) _IA64_KR_PREFIX(IA64_KR_##n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Translation registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IA64_TR_KERNEL 0 /* itr0, dtr0: maps kernel image (code & data) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IA64_TR_PALCODE 1 /* itr1: maps PALcode as required by EFI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IA64_TR_CURRENT_STACK 1 /* dtr1: maps kernel's memory- & register-stacks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IA64_TR_ALLOC_BASE 2 /* itr&dtr: Base of dynamic TR resource*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IA64_TR_ALLOC_MAX 64 /* Max number for dynamic use*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Processor status register bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IA64_PSR_BE_BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IA64_PSR_UP_BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IA64_PSR_AC_BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IA64_PSR_MFL_BIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IA64_PSR_MFH_BIT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IA64_PSR_IC_BIT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IA64_PSR_I_BIT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IA64_PSR_PK_BIT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IA64_PSR_DT_BIT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IA64_PSR_DFL_BIT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IA64_PSR_DFH_BIT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IA64_PSR_SP_BIT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IA64_PSR_PP_BIT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IA64_PSR_DI_BIT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IA64_PSR_SI_BIT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IA64_PSR_DB_BIT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IA64_PSR_LP_BIT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IA64_PSR_TB_BIT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IA64_PSR_RT_BIT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* The following are not affected by save_flags()/restore_flags(): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IA64_PSR_CPL0_BIT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IA64_PSR_CPL1_BIT 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IA64_PSR_IS_BIT 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IA64_PSR_MC_BIT 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IA64_PSR_IT_BIT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IA64_PSR_ID_BIT 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IA64_PSR_DA_BIT 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IA64_PSR_DD_BIT 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IA64_PSR_SS_BIT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IA64_PSR_RI_BIT 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IA64_PSR_ED_BIT 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IA64_PSR_BN_BIT 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IA64_PSR_IA_BIT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* A mask of PSR bits that we generally don't want to inherit across a clone2() or an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) execve(). Only list flags here that need to be cleared/set for BOTH clone2() and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) execve(). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IA64_PSR_BITS_TO_CLEAR (IA64_PSR_MFL | IA64_PSR_MFH | IA64_PSR_DB | IA64_PSR_LP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) IA64_PSR_TB | IA64_PSR_ID | IA64_PSR_DA | IA64_PSR_DD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) IA64_PSR_SS | IA64_PSR_ED | IA64_PSR_IA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IA64_PSR_BITS_TO_SET (IA64_PSR_DFH | IA64_PSR_SP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IA64_PSR_BE (__IA64_UL(1) << IA64_PSR_BE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IA64_PSR_UP (__IA64_UL(1) << IA64_PSR_UP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IA64_PSR_AC (__IA64_UL(1) << IA64_PSR_AC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IA64_PSR_MFL (__IA64_UL(1) << IA64_PSR_MFL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IA64_PSR_MFH (__IA64_UL(1) << IA64_PSR_MFH_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IA64_PSR_IC (__IA64_UL(1) << IA64_PSR_IC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IA64_PSR_I (__IA64_UL(1) << IA64_PSR_I_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IA64_PSR_PK (__IA64_UL(1) << IA64_PSR_PK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IA64_PSR_DT (__IA64_UL(1) << IA64_PSR_DT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IA64_PSR_DFL (__IA64_UL(1) << IA64_PSR_DFL_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IA64_PSR_DFH (__IA64_UL(1) << IA64_PSR_DFH_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IA64_PSR_SP (__IA64_UL(1) << IA64_PSR_SP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IA64_PSR_PP (__IA64_UL(1) << IA64_PSR_PP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IA64_PSR_DI (__IA64_UL(1) << IA64_PSR_DI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IA64_PSR_SI (__IA64_UL(1) << IA64_PSR_SI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IA64_PSR_DB (__IA64_UL(1) << IA64_PSR_DB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IA64_PSR_LP (__IA64_UL(1) << IA64_PSR_LP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IA64_PSR_TB (__IA64_UL(1) << IA64_PSR_TB_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IA64_PSR_RT (__IA64_UL(1) << IA64_PSR_RT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* The following are not affected by save_flags()/restore_flags(): */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IA64_PSR_CPL (__IA64_UL(3) << IA64_PSR_CPL0_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IA64_PSR_IS (__IA64_UL(1) << IA64_PSR_IS_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IA64_PSR_MC (__IA64_UL(1) << IA64_PSR_MC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IA64_PSR_IT (__IA64_UL(1) << IA64_PSR_IT_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IA64_PSR_ID (__IA64_UL(1) << IA64_PSR_ID_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IA64_PSR_DA (__IA64_UL(1) << IA64_PSR_DA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IA64_PSR_DD (__IA64_UL(1) << IA64_PSR_DD_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IA64_PSR_SS (__IA64_UL(1) << IA64_PSR_SS_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IA64_PSR_RI (__IA64_UL(3) << IA64_PSR_RI_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IA64_PSR_ED (__IA64_UL(1) << IA64_PSR_ED_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IA64_PSR_BN (__IA64_UL(1) << IA64_PSR_BN_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IA64_PSR_IA (__IA64_UL(1) << IA64_PSR_IA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* User mask bits: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IA64_PSR_UM (IA64_PSR_BE | IA64_PSR_UP | IA64_PSR_AC | IA64_PSR_MFL | IA64_PSR_MFH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Default Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IA64_DCR_PP_BIT 0 /* privileged performance monitor default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IA64_DCR_BE_BIT 1 /* big-endian default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IA64_DCR_LC_BIT 2 /* ia32 lock-check enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IA64_DCR_DM_BIT 8 /* defer TLB miss faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IA64_DCR_DP_BIT 9 /* defer page-not-present faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IA64_DCR_DK_BIT 10 /* defer key miss faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IA64_DCR_DX_BIT 11 /* defer key permission faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IA64_DCR_DR_BIT 12 /* defer access right faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IA64_DCR_DA_BIT 13 /* defer access bit faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IA64_DCR_DD_BIT 14 /* defer debug faults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IA64_DCR_PP (__IA64_UL(1) << IA64_DCR_PP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IA64_DCR_BE (__IA64_UL(1) << IA64_DCR_BE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IA64_DCR_LC (__IA64_UL(1) << IA64_DCR_LC_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IA64_DCR_DM (__IA64_UL(1) << IA64_DCR_DM_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IA64_DCR_DP (__IA64_UL(1) << IA64_DCR_DP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IA64_DCR_DK (__IA64_UL(1) << IA64_DCR_DK_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IA64_DCR_DX (__IA64_UL(1) << IA64_DCR_DX_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IA64_DCR_DR (__IA64_UL(1) << IA64_DCR_DR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IA64_DCR_DA (__IA64_UL(1) << IA64_DCR_DA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IA64_DCR_DD (__IA64_UL(1) << IA64_DCR_DD_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IA64_ISR_X_BIT 32 /* execute access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IA64_ISR_W_BIT 33 /* write access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IA64_ISR_R_BIT 34 /* read access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IA64_ISR_NA_BIT 35 /* non-access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IA64_ISR_SP_BIT 36 /* speculative load exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IA64_ISR_RS_BIT 37 /* mandatory register-stack exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IA64_ISR_IR_BIT 38 /* invalid register frame exception */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IA64_ISR_CODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IA64_ISR_X (__IA64_UL(1) << IA64_ISR_X_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IA64_ISR_W (__IA64_UL(1) << IA64_ISR_W_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IA64_ISR_R (__IA64_UL(1) << IA64_ISR_R_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IA64_ISR_NA (__IA64_UL(1) << IA64_ISR_NA_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IA64_ISR_SP (__IA64_UL(1) << IA64_ISR_SP_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IA64_ISR_RS (__IA64_UL(1) << IA64_ISR_RS_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IA64_ISR_IR (__IA64_UL(1) << IA64_ISR_IR_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* ISR code field for non-access instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IA64_ISR_CODE_TPA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IA64_ISR_CODE_FC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IA64_ISR_CODE_PROBE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IA64_ISR_CODE_TAK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IA64_ISR_CODE_LFETCH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IA64_ISR_CODE_PROBEF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif /* _ASM_IA64_kREGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags