^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __ASM_IA64_IOSAPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __ASM_IA64_IOSAPIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define IOSAPIC_REG_SELECT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define IOSAPIC_WINDOW 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define IOSAPIC_EOI 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IOSAPIC_VERSION 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Redirection table entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IOSAPIC_RTE_LOW(i) (0x10+i*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IOSAPIC_DEST_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Delivery mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IOSAPIC_DELIVERY_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IOSAPIC_FIXED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IOSAPIC_LOWEST_PRIORITY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IOSAPIC_PMI 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IOSAPIC_NMI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IOSAPIC_INIT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IOSAPIC_EXTINT 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Interrupt polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IOSAPIC_POLARITY_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IOSAPIC_POL_HIGH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IOSAPIC_POL_LOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Trigger mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IOSAPIC_TRIGGER_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IOSAPIC_EDGE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IOSAPIC_LEVEL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * Mask bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IOSAPIC_MASK_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IOSAPIC_VECTOR_MASK 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define NR_IOSAPICS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define iosapic_pcat_compat_init ia64_native_iosapic_pcat_compat_init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define __iosapic_read __ia64_native_iosapic_read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define __iosapic_write __ia64_native_iosapic_write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define iosapic_get_irq_chip ia64_native_iosapic_get_irq_chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) extern void __init ia64_native_iosapic_pcat_compat_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) extern struct irq_chip *ia64_native_iosapic_get_irq_chip(unsigned long trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) __ia64_native_iosapic_read(char __iomem *iosapic, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) writel(reg, iosapic + IOSAPIC_REG_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return readl(iosapic + IOSAPIC_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __ia64_native_iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) writel(reg, iosapic + IOSAPIC_REG_SELECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) writel(val, iosapic + IOSAPIC_WINDOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) writel(vector, iosapic + IOSAPIC_EOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) extern void __init iosapic_system_init (int pcat_compat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) extern int iosapic_init (unsigned long address, unsigned int gsi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) extern int iosapic_remove (unsigned int gsi_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) extern int gsi_to_irq (unsigned int gsi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern void iosapic_unregister_intr (unsigned int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) extern void iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned long polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) extern int __init iosapic_register_platform_intr (u32 int_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int gsi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) int pmi_vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 eid, u16 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long polarity,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned long trigger);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) extern void map_iosapic_to_node (unsigned int, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) # endif /* !__ASSEMBLY__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* __ASM_IA64_IOSAPIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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