Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef _ASM_IA64_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define _ASM_IA64_CACHEFLUSH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2002 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *	David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/page-flags.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define flush_dcache_page(page)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) do {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	clear_bit(PG_arch_1, &(page)->flags);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) extern void flush_icache_range(unsigned long start, unsigned long end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define flush_icache_range flush_icache_range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) extern void clflush_cache_range(void *addr, int size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define flush_icache_user_page(vma, page, user_addr, len)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) do {												\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	unsigned long _addr = (unsigned long) page_address(page) + ((user_addr) & ~PAGE_MASK);	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	flush_icache_range(_addr, _addr + (len));						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <asm-generic/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif /* _ASM_IA64_CACHEFLUSH_H */