^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ASM_IA64_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ASM_IA64_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998-2003 Hewlett-Packard Co
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * David Mosberger-Tang <davidm@hpl.hp.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 02/06/02 find_next_bit() and find_first_bit() added from Erich Focht's ia64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * O(1) scheduler patch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _LINUX_BITOPS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #error only <linux/bitops.h> can be included directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/intrinsics.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/barrier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * set_bit - Atomically set a bit in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @nr: the bit to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @addr: the address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * This function is atomic and may not be reordered. See __set_bit()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * if you do not require the atomic guarantees.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Note that @nr may be almost arbitrarily large; this function is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * restricted to acting on a single-word quantity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * The address must be (at least) "long" aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Note that there are driver (e.g., eepro100) which use these operations to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * operate on hw-defined data-structures, so we can't easily change these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * operations to force a bigger alignment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) set_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) __u32 bit, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) bit = 1 << (nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) new = old | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * __set_bit - Set a bit in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @nr: the bit to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @addr: the address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Unlike set_bit(), this function is non-atomic and may be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * If it's called on the same region of memory simultaneously, the effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * may be that only one operation succeeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __set_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *((__u32 *) addr + (nr >> 5)) |= (1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * clear_bit - Clears a bit in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @nr: Bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @addr: Address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * clear_bit() is atomic and may not be reordered. However, it does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * not contain a memory barrier, so if it is used for locking purposes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * you should call smp_mb__before_atomic() and/or smp_mb__after_atomic()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * in order to ensure changes are visible on other processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) clear_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __u32 mask, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) mask = ~(1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) new = old & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * clear_bit_unlock - Clears a bit in memory with release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @nr: Bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @addr: Address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * clear_bit_unlock() is atomic and may not be reordered. It does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * contain a memory barrier suitable for unlock type operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) clear_bit_unlock (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) __u32 mask, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) mask = ~(1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) new = old & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } while (cmpxchg_rel(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * __clear_bit_unlock - Non-atomically clears a bit in memory with release
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @nr: Bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @addr: Address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * Similarly to clear_bit_unlock, the implementation uses a store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * with release semantics. See also arch_spin_unlock().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) __clear_bit_unlock(int nr, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) __u32 * const m = (__u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) __u32 const new = *m & ~(1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ia64_st4_rel_nta(m, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * __clear_bit - Clears a bit in memory (non-atomic version)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @nr: the bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @addr: the address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Unlike clear_bit(), this function is non-atomic and may be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * If it's called on the same region of memory simultaneously, the effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * may be that only one operation succeeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) __clear_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) *((__u32 *) addr + (nr >> 5)) &= ~(1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * change_bit - Toggle a bit in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @nr: Bit to toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @addr: Address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * change_bit() is atomic and may not be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * Note that @nr may be almost arbitrarily large; this function is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * restricted to acting on a single-word quantity.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) change_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) __u32 bit, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bit = (1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) new = old ^ bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * __change_bit - Toggle a bit in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @nr: the bit to toggle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @addr: the address to start counting from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Unlike change_bit(), this function is non-atomic and may be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * If it's called on the same region of memory simultaneously, the effect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * may be that only one operation succeeds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static __inline__ void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) __change_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) *((__u32 *) addr + (nr >> 5)) ^= (1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * test_and_set_bit - Set a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @nr: Bit to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * This operation is atomic and cannot be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * It also implies the acquisition side of the memory barrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) test_and_set_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) __u32 bit, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) bit = 1 << (nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) new = old | bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return (old & bit) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * test_and_set_bit_lock - Set a bit and return its old value for lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @nr: Bit to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * This is the same as test_and_set_bit on ia64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define test_and_set_bit_lock test_and_set_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * __test_and_set_bit - Set a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @nr: Bit to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * This operation is non-atomic and can be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * If two examples of this operation race, one can appear to succeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * but actually fail. You must protect multiple accesses with a lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __test_and_set_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __u32 *p = (__u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __u32 m = 1 << (nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int oldbitset = (*p & m) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) *p |= m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return oldbitset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * test_and_clear_bit - Clear a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @nr: Bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * This operation is atomic and cannot be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * It also implies the acquisition side of the memory barrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) test_and_clear_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __u32 mask, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mask = ~(1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) new = old & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return (old & ~mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * __test_and_clear_bit - Clear a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @nr: Bit to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * This operation is non-atomic and can be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * If two examples of this operation race, one can appear to succeed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * but actually fail. You must protect multiple accesses with a lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) __test_and_clear_bit(int nr, volatile void * addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __u32 *p = (__u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __u32 m = 1 << (nr & 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int oldbitset = (*p & m) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *p &= ~m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return oldbitset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * test_and_change_bit - Change a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @nr: Bit to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * This operation is atomic and cannot be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * It also implies the acquisition side of the memory barrier.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) test_and_change_bit (int nr, volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __u32 bit, old, new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) volatile __u32 *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) CMPXCHG_BUGCHECK_DECL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) m = (volatile __u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) bit = (1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) CMPXCHG_BUGCHECK(m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) new = old ^ bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) } while (cmpxchg_acq(m, old, new) != old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return (old & bit) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * __test_and_change_bit - Change a bit and return its old value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @nr: Bit to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @addr: Address to count from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * This operation is non-atomic and can be reordered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __test_and_change_bit (int nr, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) __u32 old, bit = (1 << (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __u32 *m = (__u32 *) addr + (nr >> 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) old = *m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) *m = old ^ bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return (old & bit) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static __inline__ int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) test_bit (int nr, const volatile void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 1 & (((const volatile __u32 *) addr)[nr >> 5] >> (nr & 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * ffz - find the first zero bit in a long word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @x: The long word to find the bit in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * Returns the bit-number (0..63) of the first (least significant) zero bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Undefined if no zero exists, so code should check against ~0UL first...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ffz (unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned long result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) result = ia64_popcnt(x & (~x - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * __ffs - find first bit in word.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @x: The word to search
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * Undefined if no bit exists, so code should check against 0 first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static __inline__ unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __ffs (unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) result = ia64_popcnt((x-1) & ~x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * Return bit number of last (most-significant) bit set. Undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ia64_fls (unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) long double d = x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) long exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) exp = ia64_getf_exp(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return exp - 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * Find the last (most significant) bit set. Returns 0 for x==0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * bits are numbered from 1..32 (e.g., fls(9) == 4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static inline int fls(unsigned int t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned long x = t & 0xffffffffu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) x |= x >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) x |= x >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) x |= x >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) x |= x >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) x |= x >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ia64_popcnt(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Find the last (most significant) bit set. Undefined for x==0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * Bits are numbered from 0..63 (e.g., __fls(9) == 3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static inline unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) __fls (unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) x |= x >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) x |= x >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) x |= x >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) x |= x >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) x |= x >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) x |= x >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ia64_popcnt(x) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #include <asm-generic/bitops/fls64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #include <asm-generic/bitops/builtin-ffs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * hweightN: returns the hamming weight (i.e. the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * of bits set) of a N-bit word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static __inline__ unsigned long __arch_hweight64(unsigned long x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) result = ia64_popcnt(x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define __arch_hweight32(x) ((unsigned int) __arch_hweight64((x) & 0xfffffffful))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define __arch_hweight16(x) ((unsigned int) __arch_hweight64((x) & 0xfffful))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define __arch_hweight8(x) ((unsigned int) __arch_hweight64((x) & 0xfful))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #include <asm-generic/bitops/const_hweight.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #include <asm-generic/bitops/find.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #include <asm-generic/bitops/le.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #include <asm-generic/bitops/ext2-atomic-setbit.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #include <asm-generic/bitops/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif /* __KERNEL__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #endif /* _ASM_IA64_BITOPS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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