Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * First-level interrupt controller model for Hexagon.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/hexagon_vm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static void mask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	__vmintop_locdis((long) data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static void mask_irq_num(unsigned int irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	__vmintop_locdis((long) irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static void unmask_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	__vmintop_locen((long) data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /*  This is actually all we need for handle_fasteoi_irq  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static void eoi_irq(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	__vmintop_globen((long) data->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Power mamangement wake call. We don't need this, however,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)  * if this is absent, then an -ENXIO error is returned to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)  * msm_serial driver, and it fails to correctly initialize.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)  * This is a bug in the msm_serial driver, but, for now, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)  * work around it here, by providing this bogus handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)  * XXX FIXME!!! remove this when msm_serial is fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static int set_wake(struct irq_data *data, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static struct irq_chip hexagon_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	.name		= "HEXAGON",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	.irq_mask	= mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	.irq_unmask	= unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	.irq_set_wake	= set_wake,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	.irq_eoi	= eoi_irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)  * The hexagon core comes with a first-level interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)  * with 32 total possible interrupts.  When the core is embedded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)  * into different systems/platforms, it is typically wrapped by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)  * macro cells that provide one or more second-level interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)  * controllers that are cascaded into one or more of the first-level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)  * interrupts handled here. The precise wiring of these other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)  * irqs varies from platform to platform, and are set up & configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)  * in the platform-specific files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)  * The first-level interrupt controller is wrapped by the VM, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)  * virtualizes the interrupt controller for us.  It provides a very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)  * simple, fast & efficient API, and so the fasteoi handler is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)  * appropriate for this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __init init_IRQ(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	for (irq = 0; irq < HEXAGON_CPUINTS; irq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 		mask_irq_num(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 		irq_set_chip_and_handler(irq, &hexagon_irq_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 						 handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }